component
SN74LS374N
Public Made by Adomby adom
lingxingic Flip Flops, DIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LS374N
lingxingic · Flip Flops · DIP-20
SN74LS374N from lingxingic, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low output enable; when high, all Q outputs go to high impedance, and changes on OE do not affect the flip-flop state. |
| 2 | Q0 | tri_state | Non-inverting 3-state data output of flip-flop 1. |
| 3 | D0 | input | Data input to flip-flop 1, which must meet setup and hold times relative to the CP rising edge; internal clamp diodes allow voltages above VCC through a series resistor. |
| 4 | D1 | input | Data input to flip-flop 2, which must meet setup and hold times relative to the CP rising edge; internal clamp diodes allow voltages above VCC through a series resistor. |
| 5 | Q1 | tri_state | Non-inverting 3-state data output of flip-flop 2. |
| 6 | Q2 | tri_state | Non-inverting 3-state data output of flip-flop 3. |
| 7 | D2 | input | Data input to flip-flop 3, which must meet setup and hold times relative to the CP rising edge; internal clamp diodes allow voltages above VCC through a series resistor. |
| 8 | D3 | input | Data input to flip-flop 4, which must meet setup and hold times relative to the CP rising edge; internal clamp diodes allow voltages above VCC through a series resistor. |
| 9 | Q3 | tri_state | Non-inverting 3-state data output of flip-flop 4. |
| 10 | GND | power_in | Ground reference (0 V). |
| 11 | CP | input | Clock input; the flip-flops capture data on the low-to-high rising edge. |
| 12 | Q4 | tri_state | Non-inverting 3-state data output of flip-flop 5. |
| 13 | D4 | input | Data input to flip-flop 5, which must meet setup and hold times relative to the CP rising edge; internal clamp diodes allow voltages above VCC through a series resistor. |
| 14 | D5 | input | Data input to flip-flop 6, which must meet setup and hold times relative to the CP rising edge; internal clamp diodes allow voltages above VCC through a series resistor. |
| 15 | Q5 | tri_state | Non-inverting 3-state data output of flip-flop 6. |
| 16 | Q6 | tri_state | Non-inverting 3-state data output of flip-flop 7. |
| 17 | D6 | input | Data input to flip-flop 7, which must meet setup and hold times relative to the CP rising edge; internal clamp diodes allow voltages above VCC through a series resistor. |
| 18 | D7 | input | Data input to flip-flop 8, which must meet setup and hold times relative to the CP rising edge; internal clamp diodes allow voltages above VCC through a series resistor. |
| 19 | Q7 | tri_state | Non-inverting 3-state data output of flip-flop 8. |
| 20 | VCC | power_in | Power supply; the recommended range is 2.0 V to 6.0 V (typical 5.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | DIP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压 Supply voltage (absolute max) | VCC | -0.5 | 7 | V | 8 | ||
| 输入钳位电流 Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 8 | |
| 输出钳位电流 Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 8 | |
| 输出电流 Output current | IO | -35 | 35 | mA | -0.5V<VO<VCC+0.5V | 8 | |
| 电源电流 Supply current | ICC | 70 | mA | 8 | |||
| 地电流 Ground current | IGND | -70 | mA | 8 | |||
| 贮存温度 Storage temperature | Tstg | -65 | 150 | ℃ | 8 | ||
| 总功耗 Total power dissipation | Ptot | 500 | mW | 8 | |||
| 焊接温度 Soldering temperature, DIP | TL | 245 | ℃ | 10 秒 | 8 | ||
| 电源电压 Supply voltage (recommended) | VCC | 2 | 5 | 6 | V | 9 | |
| 输入电压 Input voltage | VI | 0 | V | 9 | |||
| 输出电压 Output voltage | VO | 0 | V | 9 | |||
| 输入上升和下降转换速率 Input rise/fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 9 | ||
| 输入上升和下降转换速率 Input rise/fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 9 | |
| 输入上升和下降转换速率 Input rise/fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 9 | ||
| 工作环境温度 Operating ambient temperature | Tamb | -40 | 125 | ℃ | 9 | ||
| 高电平输入电压 High-level input voltage | VIH | 1.5 | 1.2 | V | VCC=2.0V | 9 | |
| 高电平输入电压 High-level input voltage | VIH | 3.15 | 2.4 | V | VCC=4.5V | 9 | |
| 高电平输入电压 High-level input voltage | VIH | 4.2 | 3.2 | V | VCC=6.0V | 9 | |
| 低电平输入电压 Low-level input voltage | VIL | 0.8 | 0.5 | V | VCC=2.0V | 9 | |
| 低电平输入电压 Low-level input voltage | VIL | 2.1 | 1.35 | V | VCC=4.5V | 9 | |
| 低电平输入电压 Low-level input voltage | VIL | 2.8 | 1.8 | V | VCC=6.0V | 9 | |
| 高电平输出电压 High-level output voltage | VOH | 1.9 | 2 | V | VI=VIH或VIL；IO=-20uA；VCC=2.0V | 9 | |
| 高电平输出电压 High-level output voltage | VOH | 4.4 | 4.5 | V | VI=VIH或VIL；IO=-20uA；VCC=4.5V | 9 | |
| 高电平输出电压 High-level output voltage | VOH | 5.9 | 6 | V | VI=VIH或VIL；IO=-20uA；VCC=6.0V | 9 | |
| 高电平输出电压 High-level output voltage | VOH | 3.98 | 4.32 | V | VI=VIH或VIL；IO=-6.0mA；VCC=4.5V | 9 | |
| 高电平输出电压 High-level output voltage | VOH | 5.48 | 5.81 | V | VI=VIH或VIL；IO=-7.8mA；VCC=6.0V | 9 | |
| 低电平输出电压 Low-level output voltage | VOL | 0 | 0.1 | V | VI=VIH或VIL；IO=20uA；VCC=2.0V | 9 | |
| 低电平输出电压 Low-level output voltage | VOL | 0.15 | 0.26 | V | VI=VIH或VIL；IO=6.0mA；VCC=4.5V | 9 | |
| 低电平输出电压 Low-level output voltage | VOL | 0.16 | 0.26 | V | VI=VIH或VIL；IO=7.8mA；VCC=6.0V | 9 | |
| 输入漏电流 Input leakage current | II | -1 | 1 | uA | VI=VCC或GND；VCC=6.0V | 9 | |
| 截止状态输出电流 Off-state output current | IOZ | -1 | 1 | uA | VI=VIH或VIL；VCC=6.0V；VO=VCC或GND | 9 | |
| 静态电流 Quiescent supply current | ICC | 8 | uA | VI=VCC或GND；IO=0A；VCC=6.0V | 9 | ||
| CP到Qn的传输延时 Propagation delay CP to Qn | tpd | 165 | ns | VCC=2.0V；见图6 | 12 | ||
| CP到Qn的传输延时 Propagation delay CP to Qn | tpd | 33 | ns | VCC=4.5V；见图6 | 12 | ||
| CP到Qn的传输延时 Propagation delay CP to Qn | tpd | 18 | ns | VCC=6.0V；见图6 | 12 | ||
| OE到Qn的使能时间 Enable time OE to Qn | ten | 150 | ns | VCC=2.0V；见图7 | 12 | ||
| OE到Qn的使能时间 Enable time OE to Qn | ten | 30 | ns | VCC=4.5V；见图7 | 12 | ||
| OE到Qn的使能时间 Enable time OE to Qn | ten | 26 | ns | VCC=6.0V；见图7 | 12 | ||
| OE到Qn的失能时间 Disable time OE to Qn | tdis | 150 | ns | VCC=2.0V；见图7 | 12 | ||
| OE到Qn的失能时间 Disable time OE to Qn | tdis | 30 | ns | VCC=4.5V；见图7 | 12 | ||
| OE到Qn的失能时间 Disable time OE to Qn | tdis | 26 | ns | VCC=6.0V；见图7 | 12 | ||
| 转换时间 Transition time Qn output | tt | 60 | ns | VCC=2.0V；Qn输出；见图6 | 12 | ||
| 转换时间 Transition time Qn output | tt | 12 | ns | VCC=4.5V；Qn输出；见图6 | 12 | ||
| 转换时间 Transition time Qn output | tt | 10 | ns | VCC=6.0V；Qn输出；见图6 | 12 | ||
| 脉冲宽度 Pulse width CP high or low | tW | 80 | 19 | ns | VCC=2.0V；CP高电平或低电平；见图6 | 12 | |
| 脉冲宽度 Pulse width CP high or low | tW | 16 | 7 | ns | VCC=4.5V；CP高电平或低电平；见图6 | 12 | |
| 脉冲宽度 Pulse width CP high or low | tW | 14 | 6 | ns | VCC=6.0V；CP高电平或低电平；见图6 | 12 | |
| Dn到CP的建立时间 Setup time Dn to CP | tsu | 60 | 14 | ns | VCC=2.0V；见图6 | 12 | |
| Dn到CP的建立时间 Setup time Dn to CP | tsu | 12 | 5 | ns | VCC=4.5V；见图6 | 12 | |
| Dn到CP的建立时间 Setup time Dn to CP | tsu | 10 | 4 | ns | VCC=6.0V；见图6 | 12 | |
| Dn到CP的保持时间 Hold time Dn to CP | th | 5 | -6 | ns | VCC=2.0V；见图6 | 12 | |
| Dn到CP的保持时间 Hold time Dn to CP | th | 5 | -2 | ns | VCC=4.5V；见图6 | 12 | |
| 最大频率 Maximum clock frequency fmax | fmax | 6 | 23 | MHz | VCC=2.0V；CP输入；见图6 | 12 | |
| 最大频率 Maximum clock frequency fmax | fmax | 30 | 70 | MHz | VCC=4.5V；CP输入；见图6 | 12 | |
| 最大频率 Maximum clock frequency fmax | fmax | 35 | 83 | MHz | VCC=6.0V；CP输入；见图6 | 12 |
CAD (KiCad official)
- Symbol:
SN74LS374N - Footprint:
Package_DIP:DIP-20_W7.62mm - 3D model: DIP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74ls374n-etched.step/sn74ls374n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls374n.step/sn74ls374n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (22 pp, sha256
0330377b79f2eb40, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).