component
STD4NK60ZT4
Public Made by Adomby adom
STMicroelectronics MOSFETs, DPAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTD4NK60ZT4
STMicroelectronics · MOSFETs · DPAK
STD4NK60ZT4 from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate control input with ±30V maximum voltage, 3.00-4.50V threshold voltage, and ±10µA maximum gate-source leakage current. |
| 2 | D | output | Drain terminal with 600V maximum voltage, 4A continuous current at 25°C (2.5A at 100°C), and 2Ω maximum on-resistance at VGS=10V and ID=2A. |
| 3 | S | power_in | Source terminal and body diode cathode providing gate-source reference with 4A continuous current diode rating and 1.6V maximum forward voltage drop. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | DPAK |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS | 600 | V | 2 | |||
| Gate-source voltage | VGS | -30 | 30 | V | 2 | ||
| Drain current (continuous) | ID | 4 | A | TC = 25 °C | 2 | ||
| Drain current (continuous) | ID | 2.5 | A | TC = 100 °C | 2 | ||
| Drain current (pulsed) | IDM | 16 | A | Pulse width limited by safe operating area | 2 | ||
| Total power dissipation | PTOT | 70 | W | TC = 25 °C | 2 | ||
| Gate-source ESD (human body model) | ESD | 3 | kV | R = 1.5 kΩ, C = 100 pF | 2 | ||
| Peak diode recovery voltage slope | dv/dt | 4.5 | V/ns | ISD ≤ 4 A, di/dt ≤ 200 A/µs, VDS(peak) ≤ V(BR)DSS, VDD = 80% V(BR)DSS | 2 | ||
| Storage temperature range | Tstg | -55 | 150 | °C | 2 | ||
| Thermal resistance, junction-to-case | RthJC | 1.79 | °C/W | 2 | |||
| Thermal resistance, junction-to-ambient | RthJA | 50 | °C/W | When mounted on an 1-inch² FR-4, 2 Oz copper board | 2 | ||
| Avalanche current, repetitive or not repetitive | IAR | 4 | A | Pulse width limited by TJ max. | 2 | ||
| Single pulse avalanche energy | EAS | 120 | mJ | Starting TJ = 25 °C, ID = IAR, VDD = 50 V | 2 | ||
| Drain-source breakdown voltage | V(BR)DSS | 600 | V | ID = 1 mA, VGS = 0 V | 3 | ||
| Zero gate voltage drain current | IDSS | 1 | µA | VGS = 0 V, VDS = 600 V | 3 | ||
| Zero gate voltage drain current | IDSS | 50 | µA | VGS = 0 V, VDS = 600 V, TC = 125 °C | 3 | ||
| Gate body leakage current | IGSS | -10 | 10 | µA | VGS = ±20 V, VDS = 0 V | 3 | |
| Gate threshold voltage | VGS(th) | 3 | 3.75 | 4.5 | V | VDS = VGS, ID = 50 µA | 3 |
| Static drain-source on-resistance | RDS(on) | 1.7 | 2 | Ω | VGS = 10 V, ID = 2 A | 3 |
CAD (KiCad official)
- Symbol:
STD4NK60ZT4 - Footprint:
Package_TO_SOT_SMD:TO-252-2 - 3D model: DPAK (KiCad packages3D, STEP)
- 3D model files:
std4nk60zt4-etched.step/std4nk60zt4-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);std4nk60zt4.step/std4nk60zt4.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (18 pp, sha256
9ecf94526d1f2463, retrieved 2026-09-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).