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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74AC564PWR

Texas Instruments · Flip Flops · TSSOP-20

SN74AC564PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Output enable for all eight channels, active low; when high, the outputs are placed in the high-impedance state.
2	D1	input	Data input for channel 1, loaded into its flip-flop on the rising edge of CLK.
3	D2	input	Data input for channel 2, loaded into its flip-flop on the rising edge of CLK.
4	D3	input	Data input for channel 3, loaded into its flip-flop on the rising edge of CLK.
5	D4	input	Data input for channel 4, loaded into its flip-flop on the rising edge of CLK.
6	D5	input	Data input for channel 5, loaded into its flip-flop on the rising edge of CLK.
7	D6	input	Data input for channel 6, loaded into its flip-flop on the rising edge of CLK.
8	D7	input	Data input for channel 7, loaded into its flip-flop on the rising edge of CLK.
9	D8	input	Data input for channel 8, loaded into its flip-flop on the rising edge of CLK.
10	GND	power_in	Ground reference for the device.
11	CLK	input	Clock input for all channels; outputs update on the rising edge.
12	Q8	tri_state	Inverting 3-state output for channel 8, showing the inverse of the latched D value and high-impedance when OE is high.
13	Q7	tri_state	Inverting 3-state output for channel 7, showing the inverse of the latched D value and high-impedance when OE is high.
14	Q6	tri_state	Inverting 3-state output for channel 6, showing the inverse of the latched D value and high-impedance when OE is high.
15	Q5	tri_state	Inverting 3-state output for channel 5, showing the inverse of the latched D value and high-impedance when OE is high.
16	Q4	tri_state	Inverting 3-state output for channel 4, showing the inverse of the latched D value and high-impedance when OE is high.
17	Q3	tri_state	Inverting 3-state output for channel 3, showing the inverse of the latched D value and high-impedance when OE is high.
18	Q2	tri_state	Inverting 3-state output for channel 2, showing the inverse of the latched D value and high-impedance when OE is high.
19	Q1	tri_state	Inverting 3-state output for channel 1, showing the inverse of the latched D value and high-impedance when OE is high.
20	VCC	power_in	Positive supply; the datasheet recommends a supply range of 2 V to 6 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74AC564PWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: sn74ac564pwr-etched.step / sn74ac564pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ac564pwr.step / sn74ac564pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (27 pp, sha256 f4d529c6cf659a01, retrieved 2026-10-08, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF