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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

TPS54680MPWPEP

Texas Instruments · DC-DC Converters · HTSSOP-28-EP

TPS54680MPWPEP from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AGND	power_in	Analog ground, the return for the compensation network/output divider, slow-start capacitor, VBIAS capacitor and RT resistor; connect the PowerPAD to AGND.
2	VSENSE	input	Error amplifier inverting input, connected to the output voltage through the compensation network/output divider.
3	COMP	output	Error amplifier output; connect the frequency compensation network from COMP to VSENSE.
4	PWRGD	output	Open-drain power good output that is high when VSENSE is at or above 90% of Vref, otherwise low.
5	BOOT	power_out	Bootstrap output; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating drive for the high-side FET driver.
6	PH	output	Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor.
7	PH	output	Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor.
8	PH	output	Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor.
9	PH	output	Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor.
10	PH	output	Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor.
11	PH	output	Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor.
12	PH	output	Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor.
13	PH	output	Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor.
14	PH	output	Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor.
15	PGND	power_in	Power ground, the high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended.
16	PGND	power_in	Power ground, the high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended.
17	PGND	power_in	Power ground, the high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended.
18	PGND	power_in	Power ground, the high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended.
19	PGND	power_in	Power ground, the high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns, with a single-point connection to AGND recommended.
20	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator; bypass close to the package to PGND with a high-quality, low-ESR 10-µF ceramic capacitor.
21	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator; bypass close to the package to PGND with a high-quality, low-ESR 10-µF ceramic capacitor.
22	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator; bypass close to the package to PGND with a high-quality, low-ESR 10-µF ceramic capacitor.
23	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator; bypass close to the package to PGND with a high-quality, low-ESR 10-µF ceramic capacitor.
24	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator; bypass close to the package to PGND with a high-quality, low-ESR 10-µF ceramic capacitor.
25	VBIAS	power_out	Internal bias regulator output supplying regulated voltage to internal circuitry; bypass to AGND with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
26	TRACKIN	input	External reference input, a high-impedance input to the internal reference/multiplexer and error amplifier circuits.
27	ENA	input	Enable input; logic high enables the oscillator, PWM control and MOSFET driver circuits, and logic low disables operation and places the device in a low quiescent current state.
28	RT	input	Frequency setting resistor input; connect a resistor from RT to AGND to set the switching frequency.
29	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-28-EP
Category	Power Management (PMIC)
Pins	29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage range, VIN	VIN	3		6	V		3
Quiescent current	I(Q)	11		15.8	mA	fs = 350 kHz, RT open, PH pin open	3
Quiescent current	I(Q)	16		23.5	mA	fs = 500 kHz, RT = 100 kΩ, PH pin open	3
Quiescent current in shutdown	I(Q)	1		1.4	mA	Shutdown, ENA = 0 V	3
Start threshold voltage, UVLO		2.95		3	V		3
Stop threshold voltage, UVLO		2.7		2.8	V		3
Hysteresis voltage, UVLO		0.093		0.16	V		3
Output voltage, VBIAS	VBIAS	2.7	2.8	2.9	V	I(VBIAS) = 0	3
Vref accuracy	Vref	0.879	0.891	0.9	V		3
Internally set oscillator frequency		244	350	450	kHz	RT open	4
Externally set oscillator frequency		252	280	320	kHz	RT = 180 kΩ (1% resistor to AGND)	4
Externally set oscillator frequency		432	500	540	kHz	RT = 100 kΩ (1% resistor to AGND)	4
Externally set oscillator frequency		656	700	762	kHz	RT = 68 kΩ (1% resistor to AGND)	4
Error amplifier open loop voltage gain		90		110	dB	1 kΩ COMP to AGND	4
Error amplifier unity gain bandwidth		3		5	MHz	Parallel 10 kΩ, 160 pF COMP to AGND	4
Error amplifier common mode input voltage range		0			V	Powered by internal LDO	4
Input bias current, VSENSE		60		300	nA	VSENSE = Vref	4
Output voltage slew rate (symmetric), COMP		1	1.4	1.4	V/µs		4
PWM comparator propagation delay time, input to PH pin (excluding deadtime)		70		85	ns	10-mV overdrive	4
Enable threshold voltage, ENA		0.82	1.2	1.4	V		4
Output saturation voltage, PWRGD		0.18		0.3	V	I(sink) = 2.5 mA	4
Current limit trip point		6.5		10	A	VI = 3 V, output shorted	4
Current limit trip point		6.6		12	A	VI = 6 V, output shorted	4
Thermal shutdown trip point		135	150	165	°C		4
Power MOSFET switches rDS(on)	rDS(on)	26		47	mΩ	VI = 6 V	5
Power MOSFET switches rDS(on)	rDS(on)	36		65	mΩ	VI = 3 V	5
Input offset, TRACKIN		-2.5		2.5	mV	VSENSE = TRACKIN = 0.75 V	5
Input voltage range, TRACKIN		0			V	See (6)	5
Input voltage, VI	VI	-0.3		7	V	VIN, ENA	2
Input voltage, VI	VI	-0.3		6	V	RT	2
Input voltage, VI	VI	-0.3		4	V	VSENSE, TRACKIN	2
Input voltage, VI	VI	-0.3		17	V	BOOT	2
Output voltage, VO	VO	-0.3		7	V	VBIAS, COMP, PWRGD	2
Output voltage, VO	VO	-0.6		10	V	PH	2
Source current, COMP and VBIAS	IO			6	mA	COMP, VBIAS	2
Source current, PH	IO			12	A	PH	2
Sink current, COMP	IS			6	mA	COMP	2
Sink current, ENA and PWRGD	IS			10	mA	ENA, PWRGD	2
Voltage differential AGND to PGND		-0.3		0.3	V		2
Operating virtual junction temperature range	TJ	-55		150	°C		2
Storage temperature	Tstg	-65		150	°C		2
Lead temperature				300	°C	1.6 mm (1/16 inch) from case for 10 seconds	2
Input voltage range, VI	VI	3		6	V		2
Output voltage range (ordering table)	VO	0.9		3.3	V	M grade, per ordering information	1
Operating junction temperature range (ordering table)	TJ	-55		125	°C	M grade, TPS54680MPWPEP	1
Junction-to-ambient thermal resistance	θJA		36.1		°C/W		3
Junction-to-case (top) thermal resistance	θJCtop		15.5		°C/W		3
Junction-to-board thermal resistance	θJB		13.1		°C/W		3
Junction-to-top characterization parameter	ψJT		0.4		°C/W		3
Junction-to-board characterization parameter	ψJB		12.9		°C/W		3
Junction-to-case (bottom) thermal resistance	θJCbot		1.3		°C/W		3

CAD (KiCad official)

Symbol: TPS54680MPWPEP
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
3D model files: tps54680mpwpep-etched.step / tps54680mpwpep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54680mpwpep.step / tps54680mpwpep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (24 pp, sha256 0ffddd34db5b7a24, retrieved 2026-10-12, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF