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TPL820F33-3TR
Public Made by Adomby adom
3PEAK Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPL820F33-3TR
3PEAK · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3
TPL820F33-3TR from 3PEAK, in a SOT-23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin; connect the GND pin directly to the PCB ground plane. |
| 2 | OUT | power_out | Regulated output voltage pin (fixed 3 V, 3.3 V or 5 V); requires an effective output capacitance of 2.2 µF to 22 µF for loop stability, with 4.7 µF X5R/X7R ceramic recommended, and supplies up to 180 mA. |
| 3 | IN | power_in | Input voltage pin; operates from 3.6 V to 42 V (45 V absolute maximum), with a 2.2 µF or greater capacitor plus 0.1 µF bypass recommended at the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 3PEAK |
| Package | SOT-23-3 |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 3.6 | 42 | V | 9 | ||
| Quiescent Current | IQ | 2 | 5 | µA | IOUT = 0 mA | 9 | |
| Quiescent Current | IQ | 390 | µA | IOUT = 180 mA | 9 | ||
| VIN Under-Voltage Lock-out | UVLO | 2.9 | V | VIN rising | 9 | ||
| Output Voltage Accuracy | VOUT | -1 | 1 | % | TJ = +25°C | 9 | |
| Output Voltage Accuracy | VOUT | -2 | 2 | % | −40°C ≤ TJ ≤ +125°C | 9 | |
| Line Regulation | △VOUT | 3 | mV | VIN = VOUT (NOM) + 1 V to 42 V, or VIN ≥ 3.6 V，IOUT = 1 mA | 9 | ||
| Load Regulation | △VOUT | 20 | mV | IOUT = 1 mA to 180 mA | 9 | ||
| Dropout Voltage | VDO | 200 | 600 | mV | VIN = 0.98 × VOUT (NOM), IOUT = 50 mA | 9 | |
| Dropout Voltage | VDO | 720 | mV | VIN = 0.98 × VOUT (NOM), IOUT = 180 mA | 9 | ||
| Output Current | IOUT | 0 | 180 | mA | VOUT in regulation | 9 | |
| Output Current Limit | ICL | 180 | 800 | mA | VOUT = 0.9 × VOUT (NOM) | 9 | |
| Power Supply Rejection Ratio | PSRR | 75 | dB | IOUT = 10 mA, f = 100 Hz, COUT = 4.7 µF | 9 | ||
| Power Supply Rejection Ratio | PSRR | 65 | dB | IOUT = 10 mA, f = 1 kHz, COUT = 4.7 µF | 9 | ||
| Output Noise Voltage | VN | 110 | μVRMS | IOUT = 10 mA, BW = 10 Hz to 100 kHz | 9 | ||
| Output Noise Voltage | VN | 70 | μVRMS | IOUT = 10 mA, BW = 100 Hz to 100 kHz | 9 | ||
| Thermal Shutdown Threshold | TSD | 160 | ºC | 9 | |||
| Thermal Shutdown Hysteresis | 40 | ºC | 9 | ||||
| VIN Maximum Input Voltage | VIN | -0.3 | 45 | V | 7 | ||
| VOUT Maximum Output Voltage | VOUT | -0.3 | 6 | V | 7 | ||
| PD Maximum Operating Power Dissipation | PD | 1.5 | W | 7 | |||
| Maximum Junction Temperature | TJ | -40 | 150 | °C | 7 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 7 | ||
| Lead Temperature (Soldering) | TL | 260 | °C | Soldering, 10 sec | 7 | ||
| ESD Human Body Model | HBM | -2.5 | 2.5 | kV | ANSI/ESDA/JEDEC JS-001 | 7 | |
| ESD Charged Device Model | CDM | -2 | 2 | kV | ANSI/ESDA/JEDEC JS-002 | 7 | |
| Input Voltage | VIN | 3.6 | 42 | V | 7 | ||
| Output Voltage | VOUT | 1.2 | 5 | V | 7 | ||
| Output Current | IOUT | 0 | 180 | mA | 7 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 7 | ||
| Power Dissipation (SOT23-3 Package) | PD | 0 | 300 | mW | SOT23-3 package | 7 | |
| Junction-to-Ambient Thermal Resistance (SOT23-3) | θJA | 211 | °C/W | SOT23-3 package | 8 | ||
| Junction-to-Case Thermal Resistance (SOT23-3) | θJC | 62 | °C/W | SOT23-3 package | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitor connection, the IN pin, and the GND pin of the system must be as small as possible. • It is recommended to use wide trace lengths or thick copper weight to minimize I×R drop and heat dissipa | 16 |
CAD (KiCad official)
- Symbol:
TPL820F33-3TR - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT-23-3 (KiCad packages3D, STEP)
- 3D model files:
tpl820f33-3tr-etched.step/tpl820f33-3tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpl820f33-3tr.step/tpl820f33-3tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 3PEAK datasheet (24 pp, sha256
39671ce47bbffc12, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).