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Contents

README

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SI4967DY-T1-E3-VB

VBsemi Elec · MOSFETs · SO-8

SI4967DY-T1-E3-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of P-channel MOSFET 1 (VDS -20 V, ID -8.9 A at 10 s).
2 G1 input Gate of P-channel MOSFET 1 (VGS ±12 V max, threshold -0.4 to -1.0 V).
3 S2 passive Source of P-channel MOSFET 2 (VDS -20 V, ID -8.9 A at 10 s).
4 G2 input Gate of P-channel MOSFET 2 (VGS ±12 V max, threshold -0.4 to -1.0 V).
5 D2 passive Drain of P-channel MOSFET 2 (pins 5 and 6 are tied together as D2; RDS(on) 0.018 Ω at VGS -4.5 V).
6 D2 passive Drain of P-channel MOSFET 2 (pins 5 and 6 are tied together as D2; RDS(on) 0.018 Ω at VGS -4.5 V).
7 D1 passive Drain of P-channel MOSFET 1 (pins 7 and 8 are tied together as D1; RDS(on) 0.018 Ω at VGS -4.5 V).
8 D1 passive Drain of P-channel MOSFET 1 (pins 7 and 8 are tied together as D1; RDS(on) 0.018 Ω at VGS -4.5 V).

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate Threshold Voltage VGS(th) -0.4 -1 V VDS = VGS, ID = - 350 µA 2
Gate-Body Leakage IGSS -100 100 nA VDS = 0 V, VGS = ± 8 V 2
Zero Gate Voltage Drain Current IDSS -1 µA VDS = - 20 V, VGS = 0 V 2
Zero Gate Voltage Drain Current IDSS -5 µA VDS = - 20 V, VGS = 0 V, TJ = 55 °C 2
On-State Drain Current ID(on) -30 A VDS = - 5 V, VGS = - 4.5 V 2
Drain-Source On-State Resistance RDS(on) 0.018 Ω VGS = - 4.5 V, ID = - 8.9 A 2
Drain-Source On-State Resistance RDS(on) 0.022 Ω VGS = - 2.5 V, ID = - 8.1 A 2
Drain-Source On-State Resistance RDS(on) 0.03 Ω VGS = - 1.8 V, ID = - 3.6 A 2
Diode Forward Voltage VSD -0.7 -1.2 V IS = - 1.7 A, VGS = 0 V 2
Total Gate Charge Qg 34.5 52 nC VDS = - 10 V, VGS = - 4.5 V, ID = - 8.9 A 2
Turn-On Delay Time td(on) 25 40 ns VDD = - 10 V, RL = 6 Ω, ID ≅ - 1 A, VGEN = - 4.5 V, Rg = 6 Ω 2
Rise Time tr 46 70 ns VDD = - 10 V, RL = 6 Ω, ID ≅ - 1 A, VGEN = - 4.5 V, Rg = 6 Ω 2
Turn-Off Delay Time td(off) 230 345 ns VDD = - 10 V, RL = 6 Ω, ID ≅ - 1 A, VGEN = - 4.5 V, Rg = 6 Ω 2
Fall Time tf 155 235 ns VDD = - 10 V, RL = 6 Ω, ID ≅ - 1 A, VGEN = - 4.5 V, Rg = 6 Ω 2
Source-Drain Reverse Recovery Time trr 128 200 ns IF = - 1.7 A, dI/dt = 100 A/µs 2
Forward Transconductance gfs 26 S VDS = - 10 V, ID = - 8.9 A 2
Gate-Source Charge Qgs 5.1 nC VDS = - 10 V, VGS = - 4.5 V, ID = - 8.9 A 2
Gate-Drain Charge Qgd 9.6 nC VDS = - 10 V, VGS = - 4.5 V, ID = - 8.9 A 2
Gate Resistance Rg 9 Ω 2
Drain-Source Voltage VDS -20 V TA = 25 °C 1
Gate-Source Voltage VGS -12 12 V TA = 25 °C 1
Continuous Drain Current ID -8.9 A TJ = 150 °C, TA = 25 °C, 10 s 1
Continuous Drain Current ID -6.7 A TJ = 150 °C, TA = 25 °C, steady state 1
Continuous Drain Current ID -7.1 A TJ = 150 °C, TA = 70 °C, 10 s 1
Continuous Drain Current ID -5.4 A TJ = 150 °C, TA = 70 °C, steady state 1
Pulsed Drain Current IDM -30 A TA = 25 °C 1
Continuous Source Current (Diode Conduction) IS -1.7 A 10 s 1
Continuous Source Current (Diode Conduction) IS -0.9 A Steady state 1
Maximum Power Dissipation PD 2 W TA = 25 °C, 10 s 1
Maximum Power Dissipation PD 1.1 W TA = 25 °C, steady state 1
Maximum Power Dissipation PD 1.3 W TA = 70 °C, 10 s 1
Maximum Power Dissipation PD 0.7 W TA = 70 °C, steady state 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Junction-to-Ambient Thermal Resistance RthJA 46 62.5 °C/W t ≤ 10 s 1
Junction-to-Ambient Thermal Resistance RthJA 80 110 °C/W Steady state 1
Junction-to-Foot (Drain) Thermal Resistance RthJF 24 32 °C/W Steady state 1

CAD (KiCad official)

  • Symbol: SI4967DY-T1-E3-VB
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: si4967dy-t1-e3-vb-etched.step / si4967dy-t1-e3-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si4967dy-t1-e3-vb.step / si4967dy-t1-e3-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (8 pp, sha256 88e399916d4802e0, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF