component
XL65HVD08DR
Public Made by Adomby adom
XINLUDA RS-485 / RS-422 ICs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownXL65HVD08DR
XINLUDA · RS-485 / RS-422 ICs · SOP-8
XL65HVD08DR from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | R | output | Receive data output, driven high when VID is above -10 mV and low when VID is below -200 mV, with receiver output current limited to ±11 mA absolute maximum. |
| 2 | RE | input | Receiver enable input, active low; VIH is 2.25 V minimum and VIL is 0.8 V maximum. |
| 3 | DE | input | Driver enable input, active high; VIH is 2.25 V minimum and VIL is 0.8 V maximum, and DE and RE can be tied together as a direction control. |
| 4 | D | input | Driver data input that sets the bus output state when the driver is enabled; input voltage must stay between -0.5 V and VCC + 0.5 V. |
| 5 | GND | power_in | Local device ground, the reference potential for the transceiver and all bus voltages. |
| 6 | A | bidirectional | Driver differential output and receiver differential input, complementary to B; bus voltage limited to -9 V to 14 V with transients up to ±25 V through 100 Ω. |
| 7 | B | bidirectional | Driver differential output and receiver differential input, complementary to A; bus voltage limited to -9 V to 14 V with transients up to ±25 V through 100 Ω. |
| 8 | VCC | power_in | Supply pin, 3 V to 5.5 V recommended, with absolute maximum of -0.3 V to 6 V and a 100 nF ceramic bypass capacitor placed close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XINLUDA |
| Package | SOP-8 |
| Category | Interface |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 3 | 5.5 | V | 4 | ||
| High-level input voltage (driver, driver enable, receiver enable inputs) | VIH | 2.25 | V | Printed as '2.25 VCC' | 4 | ||
| Low-level input voltage | VIL | 0 | 0.8 | V | 4 | ||
| Input voltage at any bus terminal | VI | -7 | 12 | V | Separately or common mode | 4 | |
| Differential input voltage | VID | -12 | 12 | V | 4 | ||
| High-level output current, driver | IOH | -60 | mA | Driver | 4 | ||
| High-level output current, receiver | IOH | -8 | mA | Receiver | 4 | ||
| Low-level output current, driver | IOL | 60 | mA | Driver | 4 | ||
| Low-level output current, receiver | IOL | 8 | mA | Receiver | 4 | ||
| Operating free-air temperature | TA | -40 | 85 | °C | XL65HVD08 | 4 | |
| Supply voltage | VCC | -0.3 | 6 | V | 4 | ||
| Voltage at A or B | -9 | 14 | V | 4 | |||
| Input voltage at D, DE, R or RE | -0.5 | V | Printed max is VCC + 0.5 V | 4 | |||
| Voltage input, transient pulse, A and B | -25 | 25 | V | Through 100 Ω | 4 | ||
| Receiver output current | IO | -11 | 11 | mA | 4 | ||
| Maximum junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | TSTG | -65 | 150 | °C | 4 | ||
| Driver differential output voltage magnitude | /VOD/ | 1.5 | V | RL = 60 Ω, 375 Ω on each output to −7 V to 12 V, See Figure 7; printed max is VCC | 5 | ||
| Change in magnitude of driver differential output voltage | Δ/VOD/ | -0.2 | 0.2 | V | RL = 54 Ω | 5 | |
| Peak-to-peak driver common-mode output voltage | VOC(PP) | 0.5 | V | Center of two 27-Ω load resistors, See Figure 8 | 5 | ||
| Positive-going receiver differential input voltage threshold | VIT+ | -10 | mV | 5 | |||
| Negative-going receiver differential input voltage threshold | VIT- | -200 | mV | 5 | |||
| Receiver high-level output voltage | VOH | 2.4 | V | IOH = -8 mA | 5 | ||
| Receiver low-level output voltage | VOL | 0.4 | V | IOL = 8 mA | 5 | ||
| Driver input, driver enable, and receiver enable high-level input current | IIH | -100 | 100 | µA | 5 | ||
| Driver input, driver enable, and receiver enable low-level input current | IIL | -100 | 100 | µA | 5 | ||
| Driver short-circuit output current | IOS | -265 | 265 | mA | 7 V < VO < 12 V | 5 | |
| Bus input current (disabled driver) | II | 130 | µA | VI = 12 V | 5 | ||
| Bus input current (disabled driver) | II | -100 | µA | VI = -7 V | 5 | ||
| Supply current | ICC | 10 | mA | Receiver enabled, driver disabled, no load | 5 | ||
| Supply current | ICC | 16 | mA | Driver enabled, receiver disabled, no load | 5 | ||
| Supply current | ICC | 5 | µA | Both disabled | 5 | ||
| Driver high-to-low propagation delay time | tPHL | 18 | 40 | ns | RL = 54 Ω, CL = 50 pF, See Figure 9 | 6 | |
| Driver low-to-high propagation delay time | tPLH | 18 | 40 | ns | 6 | ||
| Driver 10%-to-90% differential output rise time | tr | 10 | 55 | ns | 6 | ||
| Driver 90%-to-10% differential output fall time | tf | 10 | 55 | ns | 6 | ||
| Driver enable time, receiver enabled | ten | 55 | ns | Receiver enabled, See Figures 4 and 5 | 6 | ||
| Driver enable time, receiver disabled | ten | 6 | µs | Receiver disabled, See Figures 4 and 5 | 6 | ||
| Driver disable time | tdis | 90 | ns | Receiver enabled, See Figures 4 and 5 | 6 | ||
| Receiver enable time, driver enabled | ten | 15 | ns | Driver enabled, See Figure 13 | 6 | ||
| Receiver enable time, driver disabled | ten | 6 | µs | Driver disabled, See Figure 14 | 6 | ||
| Receiver disable time | tdis | 20 | ns | Driver enabled, See Figure 13 | 6 | ||
| Receiver high-level output voltage hysteresis (VIT+ - VIT-) | Vhys | 35 | mV | 5 | |||
| Driver differential output pulse skew | tSK(P) | 2.5 | ns | 6 | |||
| Receiver high-to-low propagation delay time | tPHL | 70 | ns | 6 | |||
| Receiver low-to-high propagation delay time | tPLH | 70 | ns | 6 | |||
| Receiver 10%-to-90% differential output rise time | tr | 5 | ns | CL = 15 pF, See Figure 12 | 6 | ||
| Receiver 90%-to-10% differential output fall time | tf | 5 | ns | CL = 15 pF, See Figure 12 | 6 | ||
| Receiver differential output pulse skew | tSK(P) | 4.5 | ns | 6 | |||
| Junction-to-ambient thermal resistance | RθJA | 175.4 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 53.6 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 45.1 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 10.1 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 44.4 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
XL65HVD08DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
xl65hvd08dr-etched.step/xl65hvd08dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);xl65hvd08dr.step/xl65hvd08dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XINLUDA datasheet (22 pp, sha256
83ff359b36a669ac, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).