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LT3045HDD#PBF
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Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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Datasheet
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README
markdownLT3045HDD#PBF
Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-10-EP(3x3)
LT3045HDD#PBF from Analog Devices, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input supply to the regulator, which requires a bypass capacitor (4.7µF minimum) and operates from 2V to 20V, with reverse-voltage withstand relative to GND, OUTS and OUT. |
| 2 | IN | power_in | Input supply to the regulator, which requires a bypass capacitor (4.7µF minimum) and operates from 2V to 20V, with reverse-voltage withstand relative to GND, OUTS and OUT. |
| 3 | EN/UV | input | Enable/UVLO pin that shuts the part down when pulled low (shutdown quiescent current below 1µA), turns on at a 1.24V rising threshold with 130mV hysteresis, and must not be left floating (tie to IN if unused). |
| 4 | PG | output | Open-collector power-good flag that pulls low when PGFB is below 300mV, must not be driven more than 0.3V below GND, and may be floated if power good is not used. |
| 5 | ILIM | passive | Current-limit programming pin where a resistor to GND sets the limit with a 150mA•kΩ scale factor and which also provides a 0V to 300mV current monitor output; tie to GND if unused and do not drive more than 0.3V below GND. |
| 6 | PGFB | input | Power-good feedback input where PG releases high when PGFB rises above 300mV (7mV falling hysteresis), it also enables fast start-up, and it must be tied to IN if power good and fast start-up are not used and not driven more than 0.3V below GND. |
| 7 | SET | passive | Inverting error-amplifier input and regulation set-point, sourcing a precision 100µA through the external resistor so that VSET = ISET × RSET sets the output from 0V to 15V, and not to be driven more than 0.3V below GND. |
| 8 | GND | power_in | Ground connection that must be tied directly to the exposed backside pad and PCB ground for proper electrical and thermal performance. |
| 9 | OUTS | input | Output sense input to the non-inverting error amplifier that should be Kelvin-connected directly to the output capacitor and load and not driven more than 0.3V below GND. |
| 10 | OUT | power_out | Output pin supplying the load, requiring a minimum 10µF output capacitor with ESR below 20mΩ and ESL below 2nH, and not to be driven more than 0.3V below GND. |
| 11 | GND | power_in | Exposed pad, electrically GND, which must be soldered to the PCB ground to ensure proper electrical and thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-10-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | 2 | 20 | V | 3 | |||
| Minimum IN Pin Voltage | 1.78 | 2 | V | ILOAD = 500mA, VIN UVLO Rising | 3 | ||
| Output Voltage Range | 0 | 15 | V | VIN > VOUT | 3 | ||
| SET Pin Current | ISET | 99 | 100 | 101 | µA | VIN = 2V, ILOAD = 1mA, VOUT = 1.3V | 3 |
| SET Pin Current | ISET | 98 | 100 | 102 | µA | 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3) | 3 |
| Output Offset Voltage VOS (VOUT, VSET) | VOS | -1 | 1 | mV | VIN = 2V, ILOAD = 1mA, VOUT = 1.3V | 3 | |
| Output Offset Voltage VOS (VOUT, VSET) | VOS | -2 | 2 | mV | 2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3) | 3 | |
| Line Regulation: ∆ISET | ∆ISET | -2 | 0.5 | 2 | nA/V | VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V | 3 |
| Line Regulation: ∆VOS | ∆VOS | -3 | 0.5 | 3 | µV/V | VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V (Note 4) | 3 |
| Load Regulation: ∆VOS | ∆VOS | 0.1 | 0.5 | mV | ILOAD = 1mA to 500mA, VIN = 2V, VOUT = 1.3V (Note 4) | 3 | |
| Change in ISET with VSET | ISET | 30 | 400 | nA | VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA | 3 | |
| Change in VOS with VSET | VOS | 0.03 | 0.6 | mV | VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA (Note 4) | 3 | |
| Change in ISET with VSET | ISET | 150 | 600 | nA | VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA | 3 | |
| Change in VOS with VSET | VOS | 0.3 | 2 | mV | VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA (Note 4) | 3 | |
| Dropout Voltage | 220 | 330 | mV | ILOAD = 1mA, 50mA | 3 | ||
| Dropout Voltage | 220 | 350 | mV | ILOAD = 300mA (Note 5) | 3 | ||
| Dropout Voltage | 260 | 450 | mV | ILOAD = 500mA (Note 5) | 3 | ||
| GND Pin Current | 2.2 | 4 | mA | VIN = VOUT(NOMINAL) (Note 6), ILOAD = 10µA | 3 | ||
| GND Pin Current | 2.4 | 5.5 | mA | VIN = VOUT(NOMINAL) (Note 6), ILOAD = 1mA | 3 | ||
| GND Pin Current | 3.5 | 7 | mA | VIN = VOUT(NOMINAL) (Note 6), ILOAD = 50mA | 3 | ||
| GND Pin Current | 15 | 25 | mA | VIN = VOUT(NOMINAL) (Note 6), ILOAD = 500mA | 3 | ||
| Internal Current Limit | 570 | 710 | 850 | mA | VIN = 2V, VOUT = 0V | 4 | |
| Internal Current Limit | 230 | 330 | 430 | mA | VIN = 20V, VOUT = 0V | 4 | |
| Programmable Current Limit | 450 | 500 | 550 | mA | VIN = 2V, VOUT = 0V, RILIM = 300Ω | 4 | |
| Programmable Current Limit | 90 | 100 | 110 | mA | VIN = 2V, VOUT = 0V, RILIM = 1.5kΩ | 4 | |
| EN/UV Pin Threshold (Trip Point Rising, Turn-On) | 1.18 | 1.24 | 1.32 | V | VIN = 2V | 3 | |
| EN/UV Pin Current | -1 | 1 | µA | VEN/UV = 20V, VIN = 0V | 4 | ||
| EN/UV Pin Current | 8 | 15 | µA | VEN/UV = 1.24V, VIN = 20V | 4 | ||
| Quiescent Current in Shutdown (VEN/UV = 0V) | 10 | 20 | µA | VIN = 6V, TJ ≤ 150°C (H-/MP-Grade) | 4 | ||
| PGFB Trip Point (Rising) | 291 | 300 | 309 | mV | PGFB Trip Point Rising | 4 | |
| PG Output Low Voltage | 30 | 100 | mV | IPG = 100µA | 4 | ||
| PG Leakage Current | 1 | µA | VPG = 20V | 4 | |||
| Reverse Input Current | 100 | µA | VIN = -20V, VEN/UV = 0V, VOUT = 0V, VSET = 0V | 4 | |||
| Minimum Load Required | 10 | µA | VOUT < 1V | 4 | |||
| IN Pin Voltage | -22 | 22 | V | 2 | |||
| EN/UV Pin Voltage | -22 | 22 | V | 2 | |||
| IN-to-EN/UV Differential | -22 | 22 | V | 2 | |||
| PG Pin Voltage | -0.3 | 22 | V | Note 10 | 2 | ||
| ILIM Pin Voltage | -0.3 | 1 | V | Note 10 | 2 | ||
| PGFB Pin Voltage | -0.3 | 22 | V | Note 10 | 2 | ||
| SET Pin Voltage | -0.3 | 16 | V | Note 10 | 2 | ||
| SET Pin Current | -20 | 20 | mA | Note 7 | 2 | ||
| OUTS Pin Voltage | -0.3 | 16 | V | Note 10 | 2 | ||
| OUTS Pin Current | -20 | 20 | mA | Note 7 | 2 | ||
| OUT Pin Voltage | -0.3 | 16 | V | Note 10 | 2 | ||
| OUT-to-OUTS Differential | -1.2 | 1.2 | V | Note 14 | 2 | ||
| IN-to-OUT Differential | -22 | 22 | V | 2 | |||
| IN-to-OUTS Differential | -22 | 22 | V | 2 | |||
| Operating Junction Temperature Range (H-Grade) | TJ | -40 | 150 | °C | H-Grade, Note 9 | 2 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Programming Scale Factor | 150 | mA•kΩ | 2V < VIN < 20V (Note 11) | 4 | |||
| GND Pin Current | 4.3 | mA | VIN = VOUT(NOMINAL) (Note 6), ILOAD = 100mA | 3 | |||
| Internal Current Limit | 700 | mA | VIN = 12V, VOUT = 0V | 4 | |||
| Start-Up Time | 55 | ms | VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 0.47µF, VIN = 6V, VPGFB = 6V | 4 | |||
| Start-Up Time | 550 | ms | VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 4.7µF, VIN = 6V, VPGFB = 6V | 4 | |||
| Start-Up Time (Fast Start-Up to 90% of VOUT) | 10 | ms | VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 4.7µF, VIN = 6V, RPG1 = 50kΩ, RPG2 = 700kΩ | 4 | |||
| Thermal Shutdown Junction Temperature (TJ Rising) | 165 | °C | TJ Rising | 4 | |||
| Thermal Resistance Junction-to-Ambient (DD package) | θJA | 34 | °C/W | DD package | 2 | ||
| Thermal Resistance Junction-to-Case (DD package) | θJC | 5.5 | °C/W | DD package | 2 |
CAD (KiCad official)
- Symbol:
LT3045HDD#PBF - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
lt3045hdd-pbf-etched.step/lt3045hdd-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt3045hdd-pbf.step/lt3045hdd-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
79a19c48f10093eb, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).