component
TLV62568DRLR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLV62568DRLR
Texas Instruments · DC-DC Converters · SOT-563
TLV62568DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback pin for the internal control loop; connect this pin to an external feedback divider. |
| 2 | GND | power_in | Ground pin. |
| 3 | VIN | power_in | Power supply voltage input. |
| 4 | SW | power_out | Switch pin connected to the internal FET switches and inductor terminal; connect the inductor of the output filter to this pin. |
| 5 | EN | input | Device enable logic input; logic high enables the device, logic low disables the device and turns it into shutdown; do not leave floating. |
| 6 | NC | unconnected | No connection pin for TLV62568DRL; the pin can be connected to the output or left floating. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN, EN, PG voltage | VIN, EN, PG | -0.3 | 6 | V | 4 | ||
| SW voltage (DC) | SW | -0.3 | V | DC; max printed as VIN+0.3 | 4 | ||
| SW voltage (AC) | SW | -3 | 9 | V | less than 10 ns | 4 | |
| FB voltage | FB | -0.3 | 5.5 | V | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD Human-body model (HBM) | V(ESD) | -2000 | 2000 | V | HBM, per ANSI/ESDA/JEDEC JS-001; printed as ±2000 V | 4 | |
| ESD Charged-device model (CDM) | V(ESD) | -500 | 500 | V | CDM, per JEDEC JESD22-C101; printed as ±500 V | 4 | |
| Input voltage | VIN | 2.5 | 5.5 | V | 4 | ||
| Output voltage | VOUT | 0.6 | V | max printed as VIN | 4 | ||
| Output current | IOUT | 1 | A | 4 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Sink current at PG pin | ISINK_PG | 1 | mA | 4 | |||
| Shutdown current into VIN pin | ISD | 0.1 | 2 | µA | EN = 0 V | 5 | |
| Under voltage lock out (falling threshold) | VUVLO | 2.3 | 2.45 | V | VIN falling | 5 | |
| High-level threshold at EN pin | VIH | 0.95 | 1.2 | V | 2.5 V ≤ VIN ≤ 5.5 V | 5 | |
| Low-level threshold at EN pin | VIL | 0.4 | 0.85 | V | 2.5 V ≤ VIN ≤ 5.5 V | 5 | |
| Feedback regulation voltage | VFB | 0.588 | 0.6 | 0.612 | V | 5 | |
| Quiescent current into VIN pin | IQ | 35 | µA | Not switching | 5 | ||
| Under voltage lock out hysteresis | VUVLO | 100 | mV | 5 | |||
| Thermal shutdown threshold (rising) | TJSD | 150 | °C | Junction temperature rising | 5 | ||
| Thermal shutdown threshold (falling) | TJSD | 130 | °C | Junction temperature falling | 5 | ||
| Soft startup time (TLV62568DRL) | tSS | 900 | µs | 5 | |||
| High-side FET on resistance | RDS(on) | 150 | mΩ | 5 | |||
| Low-side FET on resistance | RDS(on) | 100 | mΩ | 5 | |||
| High-side FET current limit | ILIM | 1.5 | A | 5 | |||
| Switching frequency | fSW | 1.5 | MHz | VOUT = 1.8 V | 5 | ||
| Junction-to-ambient thermal resistance (DRL) | RθJA | 149.8 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance (DRL) | RθJC(top) | 45.7 | °C/W | 4 | |||
| Junction-to-board thermal resistance (DRL) | RθJB | 31.1 | °C/W | 4 | |||
| Junction-to-top characterization parameter (DRL) | ψJT | 1.3 | °C/W | 4 | |||
| Junction-to-board characterization parameter (DRL) | ψJB | 31.7 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
TLV62568DRLR - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
tlv62568drlr-etched.step/tlv62568drlr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv62568drlr.step/tlv62568drlr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
fa2ae3f5343f767f, retrieved 2026-09-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).