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SN74AHCT245N
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74AHCT245N
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · PDIP-20
SN74AHCT245N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIR | input | Direction pin (type I) that sets the transfer direction of the octal bus transceiver; the level-to-direction mapping is in a section not included in this excerpt. |
| 2 | A1 | bidirectional | A1 input/output pin of the octal bus transceiver, a bidirectional data line on the A bus. |
| 3 | A2 | bidirectional | A2 input/output pin of the octal bus transceiver, a bidirectional data line on the A bus. |
| 4 | A3 | bidirectional | A3 input/output pin of the octal bus transceiver, a bidirectional data line on the A bus. |
| 5 | A4 | bidirectional | A4 input/output pin of the octal bus transceiver, a bidirectional data line on the A bus. |
| 6 | A5 | bidirectional | A5 input/output pin of the octal bus transceiver, a bidirectional data line on the A bus. |
| 7 | A6 | bidirectional | A6 input/output pin of the octal bus transceiver, a bidirectional data line on the A bus. |
| 8 | A7 | bidirectional | A7 input/output pin of the octal bus transceiver, a bidirectional data line on the A bus. |
| 9 | A8 | bidirectional | A8 input/output pin of the octal bus transceiver, a bidirectional data line on the A bus. |
| 10 | GND | power_in | Ground pin for the device. |
| 11 | B8 | bidirectional | B8 input/output pin of the octal bus transceiver, a bidirectional data line on the B bus. |
| 12 | B7 | bidirectional | B7 input/output pin of the octal bus transceiver, a bidirectional data line on the B bus. |
| 13 | B6 | bidirectional | B6 input/output pin of the octal bus transceiver, a bidirectional data line on the B bus. |
| 14 | B5 | bidirectional | B5 input/output pin of the octal bus transceiver, a bidirectional data line on the B bus. |
| 15 | B4 | bidirectional | B4 input/output pin of the octal bus transceiver, a bidirectional data line on the B bus. |
| 16 | B3 | bidirectional | B3 input/output pin of the octal bus transceiver, a bidirectional data line on the B bus. |
| 17 | B2 | bidirectional | B2 input/output pin of the octal bus transceiver, a bidirectional data line on the B bus. |
| 18 | B1 | bidirectional | B1 input/output pin of the octal bus transceiver, a bidirectional data line on the B bus. |
| 19 | OE | input | Output Enable input that controls the transceiver outputs; the active level is not stated in this excerpt. |
| 20 | VCC | power_in | Positive supply pin; the recommended supply range is 4.5 V to 5.5 V (stated on page 4). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5.5 | V | 4 | ||
| High-level input voltage | VIH | 2 | V | 4 | |||
| Low-level input voltage | VIL | 0.8 | V | 4 | |||
| Input voltage | VI | 0 | 5.5 | V | 4 | ||
| Output voltage | VO | 0 | V | 4 | |||
| High-level output current | IOH | -8 | mA | 4 | |||
| Low-level output current | IOL | 8 | mA | 4 | |||
| Input transition rise and fall rate | Δt/Δv | 20 | ns/V | 4 | |||
| Operating free-air temperature | TA | -40 | 125 | °C | SN74AHCT245 -40°C to 125°C | 4 | |
| Supply voltage range | VCC | -0.5 | 7 | V | 4 | ||
| Input voltage range | VI | -0.5 | 7 | V | Control inputs | 4 | |
| Output voltage range | VO | -0.5 | V | 4 | |||
| Input clamp current | IIK | -20 | mA | VI < 0; control inputs | 4 | ||
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 4 | |
| Continuous output current | IO | -25 | 25 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -75 | 75 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| High-level output voltage | VOH | 4.4 | 4.5 | V | IOH = -50 µA; VCC = 4.5 V | 5 | |
| High-level output voltage | VOH | 3.7 | 3.94 | V | IOH = -8 mA; VCC = 4.5 V | 5 | |
| Low-level output voltage | VOL | 0.1 | V | IOL = 50 µA; VCC = 4.5 V | 5 | ||
| Low-level output voltage | VOL | 0.36 | 0.44 | V | IOH = 8 mA; VCC = 4.5 V | 5 | |
| Input current (OE or DIR) | II | -1 | 1 | µA | VI = 5.5 V or GND; VCC = 0 to 5.5 V | 5 | |
| Off-state output current (A or B inputs) | IOZ | -2.5 | 2.5 | µA | VO = VCC or GND; VCC = 5.5 V | 5 | |
| Quiescent supply current | ICC | 4 | 40 | µA | VI = VCC or GND; IO = 0; VCC = 5.5 V | 5 | |
| Additional supply current per input | ΔICC | 1.35 | 1.5 | mA | One input at 3.4 V, other inputs at VCC or GND; VCC = 5.5 V | 5 | |
| Input capacitance (OE or DIR) | Ci | 2.5 | 10 | pF | VI = VCC or GND; VCC = 5 V | 5 | |
| Input/output capacitance (A or B inputs) | Cio | 4 | pF | VI = VCC or GND; VCC = 5 V | 5 | ||
| Propagation delay A or B to B or A (tPLH) | tPLH | 1 | 4.5 | 10 | ns | CL = 15 pF; VCC = 5 V ± 0.5 V | 6 |
| Propagation delay A or B to B or A (tPHL) | tPHL | 1 | 4.5 | 10 | ns | CL = 15 pF; VCC = 5 V ± 0.5 V | 6 |
| Output enable time OE to A or B (tPZH) | tPZH | 1 | 8.9 | 16 | ns | CL = 15 pF; VCC = 5 V ± 0.5 V | 6 |
| Output enable time OE to A or B (tPZL) | tPZL | 1 | 8.9 | 16 | ns | CL = 15 pF; VCC = 5 V ± 0.5 V | 6 |
| Output disable time OE to A or B (tPHZ) | tPHZ | 1 | 9.2 | 16.5 | ns | CL = 15 pF; VCC = 5 V ± 0.5 V | 6 |
| Output disable time OE to A or B (tPLZ) | tPLZ | 1 | 9.2 | 16.5 | ns | CL = 15 pF; VCC = 5 V ± 0.5 V | 6 |
| Propagation delay A or B to B or A (tPLH) | tPLH | 1 | 5.3 | 11 | ns | CL = 50 pF; VCC = 5 V ± 0.5 V | 6 |
| Propagation delay A or B to B or A (tPHL) | tPHL | 1 | 5.3 | 11 | ns | CL = 50 pF; VCC = 5 V ± 0.5 V | 6 |
| Output enable time OE to A or B (tPZH) | tPZH | 1 | 9.7 | 17 | ns | CL = 50 pF; VCC = 5 V ± 0.5 V | 6 |
| Output enable time OE to A or B (tPZL) | tPZL | 1 | 9.7 | 17 | ns | CL = 50 pF; VCC = 5 V ± 0.5 V | 6 |
| Output disable time OE to A or B (tPHZ) | tPHZ | 1 | 10 | 17.5 | ns | CL = 50 pF; VCC = 5 V ± 0.5 V | 6 |
| Output disable time OE to A or B (tPLZ) | tPLZ | 1 | 10 | 17.5 | ns | CL = 50 pF; VCC = 5 V ± 0.5 V | 6 |
| Output skew | tsk(o) | 1 | ns | CL = 50 pF | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 51.5 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 38.2 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 32.4 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 24.6 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 32.3 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
SN74AHCT245N - Footprint:
Package_DIP:DIP-20_W7.62mm - 3D model: PDIP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74ahct245n-etched.step/sn74ahct245n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ahct245n.step/sn74ahct245n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
0929f5fab514d31a, retrieved 2026-10-16, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).