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MCP3008T-E
Public Made by Adomby adom
Microchip Tech Analog To Digital Converters (ADCs), SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMCP3008T-E
Microchip Tech · Analog To Digital Converters (ADCs) · SOIC-16
MCP3008T-E from Microchip Tech, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CH0 | input | Analog input channel 0, programmable as single-ended or as part of a pseudo-differential pair. |
| 2 | CH1 | input | Analog input channel 1, programmable as single-ended or as part of a pseudo-differential pair. |
| 3 | CH2 | input | Analog input channel 2, programmable as single-ended or as part of a pseudo-differential pair. |
| 4 | CH3 | input | Analog input channel 3, programmable as single-ended or as part of a pseudo-differential pair. |
| 5 | CH4 | input | Analog input channel 4, programmable as single-ended or as part of a pseudo-differential pair. |
| 6 | CH5 | input | Analog input channel 5, programmable as single-ended or as part of a pseudo-differential pair. |
| 7 | CH6 | input | Analog input channel 6, programmable as single-ended or as part of a pseudo-differential pair. |
| 8 | CH7 | input | Analog input channel 7, programmable as single-ended or as part of a pseudo-differential pair. |
| 9 | DGND | power_in | Digital ground connection to internal digital circuitry. |
| 10 | CS/SHDN | input | Chip select/shutdown input; pulled low it initiates communication, pulled high it ends a conversion and enters low-power standby, and it must be high between conversions. |
| 11 | DIN | input | SPI serial data input used to load channel configuration data into the device. |
| 12 | DOUT | output | SPI serial data output that shifts out the A/D conversion result, changing on the falling clock edge. |
| 13 | SCLK | input | SPI clock input used to initiate a conversion and clock out each bit of the conversion. |
| 14 | AGND | power_in | Analog ground connection to internal analog circuitry. |
| 15 | VREF | power_in | Reference voltage input. |
| 16 | VDD | power_in | +2.7V to 5.5V power supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Integral Nonlinearity | INL | -1 | 0.5 | 1 | LSB | 3 | |
| Differential Nonlinearity | DNL | -1 | 0.25 | 1 | LSB | No missing codes over temperature | 3 |
| Offset Error | OSER | -1.95 | 0.87 | 1.95 | LSB | -40°C to +125°C (Note 5) | 3 |
| Gain Error | GER | -1 | 0.06 | 1 | LSB | 3 | |
| Conversion Time | tCONV | 10 | clock cycles | 3 | |||
| Throughput Rate | fSAMPLE | 200 | ksps | VDD = VREF = 5V | 3 | ||
| Throughput Rate | fSAMPLE | 130 | ksps | VDD = VREF = 3.3V (Note 1) | 3 | ||
| Throughput Rate | fSAMPLE | 75 | ksps | VDD = VREF = 2.7V | 3 | ||
| Reference Input Voltage Range | 0.25 | V | Note 2; upper limit VDD | 3 | |||
| Reference Current Drain, operation | 100 | 150 | µA | During operation | 3 | ||
| Reference Current Drain, idle | 0.001 | 3 | µA | Idle state, CS = VDD = 5V | 3 | ||
| Analog Input Leakage Current | -1 | 0.001 | 1 | µA | 4 | ||
| Input Voltage Range for IN- in pseudo-differential mode | -100 | 100 | mV | VSS - 100 to VSS + 100 | 4 | ||
| High Level Input Voltage | VIH | 0.7 | V | 0.7 VDD | 4 | ||
| Low Level Input Voltage | VIL | 0.3 | V | 0.3 VDD | 4 | ||
| High Level Output Voltage | VOH | 4.1 | V | IOH = -1 mA, VDD = 4.5V | 4 | ||
| Low Level Output Voltage | VOL | 0.4 | V | IOL = 1 mA, VDD = 4.5V | 4 | ||
| Input Leakage Current | ILI | -10 | 10 | µA | VIN = VSS or VDD | 4 | |
| Output Leakage Current | ILO | -10 | 10 | µA | VOUT = VSS or VDD | 4 | |
| Pin Capacitance (All Inputs/Outputs) | CIN, COUT | 10 | pF | VDD = 5.0V (Note 1), TA = 25°C, f = 1 MHz | 4 | ||
| Clock Frequency | fSCLK | 3.6 | MHz | VDD = 5V (Note 3) | 4 | ||
| Clock Frequency | fSCLK | 1.35 | MHz | VDD = 2.7V (Note 3) | 4 | ||
| Clock High Time | tHI | 125 | ns | 4 | |||
| Clock Low Time | tLO | 125 | ns | 4 | |||
| CS Fall To First Rising SCLK Edge | tSUCS | 100 | ns | 4 | |||
| CS Fall To Falling SCLK Edge | tCSD | 0 | ns | 4 | |||
| Data Input Setup Time | tSU | 50 | ns | 4 | |||
| Data Input Hold Time | tHD | 50 | ns | 4 | |||
| SCLK Fall To Output Data Valid | tDO | 125 | ns | VDD = 5V, See Figure 1-2 | 4 | ||
| SCLK Fall To Output Data Valid | tDO | 200 | ns | VDD = 2.7V, See Figure 1-2 | 4 | ||
| SCLK Fall To Output Enable | tEN | 125 | ns | VDD = 5V, See Figure 1-2 | 4 | ||
| SCLK Fall To Output Enable | tEN | 200 | ns | VDD = 2.7V, See Figure 1-2 | 4 | ||
| CS Rise To Output Disable | tDIS | 100 | ns | See Test Circuits, Figure 1-2 | 4 | ||
| CS Disable Time | tCSH | 270 | ns | 4 | |||
| DOUT Rise Time | tR | 100 | ns | See Test Circuits, Figure 1-2 (Note 1) | 4 | ||
| DOUT Fall Time | tF | 100 | ns | See Test Circuits, Figure 1-2 (Note 1) | 4 | ||
| Operating Voltage | VDD | 2.7 | 5.5 | V | 5 | ||
| Operating Current | IDD | 425 | 550 | µA | VDD = VREF = 5V, DOUT unloaded | 5 | |
| Operating Current | IDD | 287 | µA | VDD = VREF = 3.3V, fSAMPLE = 130 kSPS, DOUT unloaded | 5 | ||
| Operating Current | IDD | 216 | µA | VDD = VREF = 2.7V, fSAMPLE = 75 kSPS, DOUT unloaded | 5 | ||
| Standby Current | IDDS | 0.005 | 2 | µA | CS = VDD = 5.0V | 5 | |
| Specified Temperature Range | TA | -40 | 85 | °C | As printed in temperature table; features list -40 to +125 for SOIC | 5 | |
| Operating Temperature Range | TA | -40 | 85 | °C | As printed in temperature table; features list -40 to +125 for SOIC | 5 | |
| Storage Temperature Range | TA | -65 | 150 | °C | 5 | ||
| Thermal Resistance, 16L-SOIC | θJA | 90 | °C/W | 5 | |||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| Ambient temperature with power applied | -65 | 150 | °C | 3 | |||
| Soldering temperature of leads | 300 | °C | 10 seconds | 3 | |||
| ESD protection CDM | 2 | kV | All pins, -40°C to +125°C | 3 | |||
| ESD protection HBM | 4 | kV | All pins, -40°C to +125°C | 3 | |||
| Resolution | 10 | bits | 3 | ||||
| Analog Input Sample Time | tSAMPLE | 1.5 | clock cycles | 3 | |||
| Total Harmonic Distortion | THD | -76 | dB | VIN = 0.1V to 4.9V@1 kHz | 3 | ||
| Signal-to-Noise and Distortion | SINAD | 61 | dB | VIN = 0.1V to 4.9V@1 kHz | 3 | ||
| Spurious Free Dynamic Range | SFDR | 78 | dB | VIN = 0.1V to 4.9V@1 kHz | 3 | ||
| Switch Resistance | 1000 | Ω | See Figure 4-1 | 4 | |||
| Sample Capacitor | 20 | pF | See Figure 4-1 | 4 |
CAD (KiCad official)
- Symbol:
MCP3008T-E - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
mcp3008t-e-etched.step/mcp3008t-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp3008t-e.step/mcp3008t-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (42 pp, sha256
26a503d76279cc10, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).