component
CS1180
Public Made by Adomby adom
CHIPSEA Analog To Digital Converters (ADC), SSOP-16-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCS1180
CHIPSEA · Analog To Digital Converters (ADC) · SSOP-16-208mil
CS1180 from CHIPSEA, in a SSOP-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DGND | power_in | Digital ground pin for the CS1180 digital section. |
| 2 | MCLK | input | Master clock input for 1-10 MHz; an external clock is applied here, and when a crystal is used 10-20 pF capacitors are required on MCLK and XTAL. |
| 3 | XTAL | passive | Crystal driver pin, requiring a 10-20 pF load capacitor to MCLK when a crystal is used, and left floating when an external clock is driven into MCLK. |
| 4 | DGND | power_in | Digital ground pin for the CS1180 digital section. |
| 5 | REFP | input | Positive analog reference voltage input; the reference VREF=REFP−REFN must not exceed the chip supply voltage. |
| 6 | REFN | input | Negative analog reference voltage input paired with REFP to form VREF, which must not exceed the chip supply voltage. |
| 7 | AIN0 | input | Positive analog input (AIN+) of the differential input; with the input buffer off the input range is AGND−0.1 V to AVDD+0.1 V. |
| 8 | AIN1 | input | Negative analog input (AIN−) of the differential input, with full-scale defined as (AIN+)−(AIN−). |
| 9 | AGND | power_in | Analog ground pin for the CS1180 analog section. |
| 10 | AVDD | power_in | Analog supply voltage, specified at 2.7 V to 5.25 V; absolute maximum AVDD to AGND is 6 V. |
| 11 | CS | input | Chip select, active low; it must be held low for the whole communication, and the SPI bus is reset when CS goes high. |
| 12 | SDI | input | Serial data input for the SPI slave interface, sampled on SCLK edges. |
| 13 | SDO | tri_state | Serial data output for the SPI slave interface, which is high impedance when not in use so SDI and SDO can be tied together as a bidirectional bus. |
| 14 | SCLK | input | Serial clock input with Schmitt-trigger input used to sample SDI and SDO, which must be kept clean to avoid sampling errors. |
| 15 | DRDY | output | Data ready output, active low, which goes low when new conversion data is available in the DOR register. |
| 16 | DVDD | power_in | Digital supply voltage, specified at 2.7 V to 5.25 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CHIPSEA |
| Package | SSOP-16-208mil |
| Category | Data Acquisition |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply voltage AVDD (absolute maximum) | AVDD | -0.3 | 6 | V | AVDD to AGND | 8 | |
| Digital supply voltage DVDD (absolute maximum) | DVDD | -0.3 | 6 | V | DVDD to DGND | 8 | |
| Ground difference DGND to AGND (absolute maximum) | DVGND | -0.3 | 0.3 | V | DGND to AGND | 8 | |
| Input current, momentary | 100 | mA | Input Current momentary | 8 | |||
| Input current, continuous | 10 | mA | Input Current continuous | 8 | |||
| Digital input voltage (max printed as DVDD+0.3) | -0.3 | V | 8 | ||||
| Digital output voltage (max printed as DVDD+0.3) | -0.3 | V | Digital Output Voltage to DGND | 8 | |||
| Max. junction temperature | 150 | oC | Max. Junction Temperature | 8 | |||
| Storage temperature | -60 | 150 | oC | Storage Temperature | 8 | ||
| Lead temperature (soldering) | 300 | oC | Soldering, 10s | 8 | |||
| Operating temperature | -40 | 85 | oC | Operating Temperature | 8 | ||
| Analog supply voltage AVDD (pin range) | AVDD | 2.7 | 5.25 | V | Pin 10 AVDD: analog supply voltage 2.7V~5.25V | 9 | |
| Digital supply voltage DVDD (pin range) | DVDD | 2.7 | 5.25 | V | Pin 16 DVDD: digital supply voltage 2.7~5.25V | 9 | |
| Master clock input frequency MCLK | MCLK | 1 | 10 | MHz | Pin 2 MCLK: main clock input 1~10MHz | 9 | |
| External reference differential voltage VREF (RAN=0) | VREF | 2.5 | V | AVDD=5 V, RAN=0 | 15 | ||
| External reference differential voltage VREF (RAN=1) | VREF | 5 | V | AVDD=5 V, RAN=1 | 15 | ||
| External reference differential voltage VREF (RAN=0) | VREF | 1.25 | V | AVDD=3.0 V, RAN=0 | 15 | ||
| External reference differential voltage VREF (RAN=1) | VREF | 2.5 | V | AVDD=3.0 V, RAN=1 | 15 | ||
| Oscillator frequency fosc | fosc | 1 | 5 | MHz | 13 | ||
| High-level input current IIH | IIH | 10 | uA | VI=DVDD | 8 | ||
| Low-level input current IIL | IIL | -10 | uA | VI=DGND | 8 | ||
| PGA gain range (AVDD=5V table) | 1 | 128 | Table 4 AVDD=5V: PGA 可选增益范围 | 10 | |||
| Integral nonlinearity INL (AVDD=5V table) | -0.0015 | 0.0015 | % of FS | Table 4 AVDD=5V: 积分线性度 | 10 | ||
| Power supply rejection ratio PSRR (AVDD=5V table) | 80 | 95 | dB | Table 4 AVDD=5V: 直流 (DC) | 10 | ||
| Reference voltage VREF (AVDD=5V table, RAN=0) | VREF | 0.1 | 2.5 | 2.6 | V | Table 4 AVDD=5V: RAN = 0 | 10 |
| Reference voltage VREF (AVDD=5V table, RAN=1) | VREF | 0 | 2.5 | V | Table 4 AVDD=5V: RAN = 1 (max printed as AVDD) | 10 | |
| REFP, REFN input range (AVDD=5V table, RAN=0) | 0 | V | Table 4 AVDD=5V: RAN = 0 (max printed as AVDD) | 10 | |||
| REFP, REFN input range (AVDD=5V table, RAN=1) | 0.1 | V | Table 4 AVDD=5V: RAN = 1 (max printed as AVDD) | 10 | |||
| Power supply voltage AVDD (AVDD=5V table) | AVDD | 4.75 | 5.25 | V | Table 4 AVDD=5V: 电源电压 AVDD | 10 | |
| PGA gain range (AVDD=3V table) | 1 | 128 | Table 5 AVDD=3V: PGA 可选增益范围 | 11 | |||
| Integral nonlinearity INL (AVDD=3V table) | -0.0015 | 0.0015 | % of FS | Table 5 AVDD=3V: 积分线性度 | 11 | ||
| Power supply rejection ratio PSRR (AVDD=3V table) | 75 | 90 | dB | Table 5 AVDD=3V: 直流 (DC) | 11 | ||
| Reference voltage VREF (AVDD=3V table, RAN=0) | VREF | 0.1 | 1.25 | 1.3 | V | Table 5 AVDD=3V: RAN = 0 | 11 |
| Reference voltage VREF (AVDD=3V table, RAN=1) | VREF | 0 | 2.5 | 2.6 | V | Table 5 AVDD=3V: RAN = 1 | 11 |
| REFP, REFN input range (AVDD=3V table, RAN=0) | 0 | V | Table 5 AVDD=3V: RAN = 0 (max printed as AVDD) | 11 | |||
| REFP, REFN input range (AVDD=3V table, RAN=1) | 0.1 | V | Table 5 AVDD=3V: RAN = 1 (max printed as AVDD) | 11 | |||
| Power supply voltage AVDD (AVDD=3V table) | AVDD | 2.7 | 3.3 | V | Table 5 AVDD=3V: 电源电压 AVDD | 11 | |
| SDO three-state delay from SCLK edge tdsot | tdsot | 6 | 10 | tosc cycles | SDO 变为三态与 SCLK 时钟沿的延迟 | 13 |
CAD (KiCad official)
- Symbol:
CS1180 - Footprint:
Package_SO:SSOP-16_5.3x6.2mm_P0.65mm - 3D model: SSOP-16-208mil (KiCad packages3D, STEP)
- 3D model files:
cs1180-etched.step/cs1180-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cs1180.step/cs1180.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CHIPSEA datasheet (30 pp, sha256
5eb0593f504c446f, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).