C8051F121-GQR from SILICON LABS, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CP1-	input	Comparator 1 inverting input.
2	CP1+	input	Comparator 1 non-inverting input.
3	CP0-	input	Comparator 0 inverting input.
4	CP0+	input	Comparator 0 non-inverting input.
5	AGND	power_in	Analog ground; must be tied to ground.
6	AV+	power_in	Analog supply voltage; must be tied to +2.7 to +3.6 V.
7	VREF	power_in	Bandgap voltage reference output (all devices); DAC voltage reference input on C8051F121/3/5/7.
8	VREFA	input	ADC0 and ADC2 voltage reference input.
9	AIN0.0	input	ADC0 input channel 0.
10	AIN0.1	input	ADC0 input channel 1.
11	AIN0.2	input	ADC0 input channel 2.
12	AIN0.3	input	ADC0 input channel 3.
13	AIN0.4	input	ADC0 input channel 4.
14	AIN0.5	input	ADC0 input channel 5.
15	AIN0.6	input	ADC0 input channel 6.
16	AIN0.7	input	ADC0 input channel 7.
17	XTAL1	input	Crystal input, the return for the internal oscillator circuit for a crystal or ceramic resonator; becomes the system clock if overdriven by an external CMOS clock.
18	XTAL2	output	Crystal output; excitation driver for a crystal or ceramic resonator.
19	MONEN	input	VDD monitor enable; tied high enables the internal VDD monitor that resets the system when VDD < VRST, tied low disables it, and must be tied high or low.
20	AIN2.7/A15/P1.7	bidirectional	ADC2 input channel 7, external memory address bit 15 (non-multiplexed mode), or Port 1.7.
21	AIN2.6/A14/P1.6	bidirectional	ADC2 input channel 6, external memory address bit 14 (non-multiplexed mode), or Port 1.6.
22	AIN2.5/A13/P1.5	bidirectional	ADC2 input channel 5, external memory address bit 13 (non-multiplexed mode), or Port 1.5.
23	AIN2.4/A12/P1.4	bidirectional	ADC2 input channel 4, external memory address bit 12 (non-multiplexed mode), or Port 1.4.
24	VDD	power_in	Digital supply voltage; must be tied to +2.7 to +3.6 V.
25	DGND	power_in	Digital ground; must be tied to ground.
26	AIN2.3/A11/P1.3	bidirectional	ADC2 input channel 3, external memory address bit 11 (non-multiplexed mode), or Port 1.3.
27	AIN2.2/A10/P1.2	bidirectional	ADC2 input channel 2, external memory address bit 10 (non-multiplexed mode), or Port 1.2.
28	AIN2.1/A9/P1.1	bidirectional	ADC2 input channel 1, external memory address bit 9 (non-multiplexed mode), or Port 1.1.
29	AIN2.0/A8/P1.0	bidirectional	ADC2 input channel 0, external memory address bit 8 (non-multiplexed mode), or Port 1.0.
30	A15m/A7/P2.7	bidirectional	External memory address bit 15 (multiplexed) or bit 7 (non-multiplexed), or Port 2.7.
31	A14m/A6/P2.6	bidirectional	External memory address bit 14 (multiplexed) or bit 6 (non-multiplexed), or Port 2.6.
32	A13m/A5/P2.5	bidirectional	External memory address bit 13 (multiplexed) or bit 5 (non-multiplexed), or Port 2.5.
33	A12m/A4/P2.4	bidirectional	External memory address bit 12 (multiplexed) or bit 4 (non-multiplexed), or Port 2.4.
34	A11m/A3/P2.3	bidirectional	External memory address bit 11 (multiplexed) or bit 3 (non-multiplexed), or Port 2.3.
35	A10m/A2/P2.2	bidirectional	External memory address bit 10 (multiplexed) or bit 2 (non-multiplexed), or Port 2.2.
36	A9m/A1/P2.1	bidirectional	External memory address bit 9 (multiplexed) or bit 1 (non-multiplexed), or Port 2.1.
37	A8m/A0/P2.0	bidirectional	External memory address bit 8 (multiplexed) or bit 0 (non-multiplexed), or Port 2.0.
38	AD7/D7/P3.7	bidirectional	External memory address/data bit 7 (multiplexed) or data bit 7 (non-multiplexed), or Port 3.7.
39	AD6/D6/P3.6	bidirectional	External memory address/data bit 6 (multiplexed) or data bit 6 (non-multiplexed), or Port 3.6.
40	DGND	power_in	Digital ground; must be tied to ground.
41	VDD	power_in	Digital supply voltage; must be tied to +2.7 to +3.6 V.
42	AD5/D5/P3.5	bidirectional	External memory address/data bit 5 (multiplexed) or data bit 5 (non-multiplexed), or Port 3.5.
43	AD4/D4/P3.4	bidirectional	External memory address/data bit 4 (multiplexed) or data bit 4 (non-multiplexed), or Port 3.4.
44	AD3/D3/P3.3	bidirectional	External memory address/data bit 3 (multiplexed) or data bit 3 (non-multiplexed), or Port 3.3.
45	AD2/D2/P3.2	bidirectional	External memory address/data bit 2 (multiplexed) or data bit 2 (non-multiplexed), or Port 3.2.
46	AD1/D1/P3.1	bidirectional	External memory address/data bit 1 (multiplexed) or data bit 1 (non-multiplexed), or Port 3.1.
47	AD0/D0/P3.0	bidirectional	External memory address/data bit 0 (multiplexed) or data bit 0 (non-multiplexed), or Port 3.0.
48	WR/P0.7	bidirectional	/WR strobe for the external memory bus, or Port 0.7.
49	RD/P0.6	bidirectional	/RD strobe for the external memory bus, or Port 0.6.
50	ALE/P0.5	bidirectional	ALE strobe for the external memory address bus (multiplexed mode), or Port 0.5.
51	P0.4	bidirectional	Port 0.4 general-purpose I/O or crossbar-assigned digital function.
52	P0.3	bidirectional	Port 0.3 general-purpose I/O or crossbar-assigned digital function.
53	P0.2	bidirectional	Port 0.2 general-purpose I/O or crossbar-assigned digital function.
54	P0.1	bidirectional	Port 0.1 general-purpose I/O or crossbar-assigned digital function (RX0 when UART0 is enabled).
55	P0.0	bidirectional	Port 0.0 general-purpose I/O or crossbar-assigned digital function (TX0 when UART0 is enabled).
56	DGND	power_in	Digital ground; must be tied to ground.
57	VDD	power_in	Digital supply voltage; must be tied to +2.7 to +3.6 V.
58	TMS	input	JTAG test mode select with internal pullup.
59	TCK	input	JTAG test clock with internal pullup.
60	TDI	input	JTAG test data input with internal pullup, latched on the rising edge of TCK.
61	TDO	tri_state	JTAG test data output with internal pullup, shifted out on the falling edge of TCK; tri-state driver.
62	RST	bidirectional	Device reset; open-drain output of internal VDD monitor, driven low when VDD < VRST and MONEN is high; an external source can force a reset by driving it low.
63	DAC1	output	Digital-to-analog converter 1 voltage output.
64	DAC0	output	Digital-to-analog converter 0 voltage output.

Key specifications

Parameter	Value
Manufacturer	SILICON LABS
Package	TQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog Supply Voltage	AV+	2.7	3	3.6	V	SYSCLK = 0 to 50 MHz	39
Analog Supply Voltage	AV+	3	3.3	3.6	V	SYSCLK > 50 MHz	39
Digital Supply Voltage	VDD	2.7	3	3.6	V	SYSCLK = 0 to 50 MHz	39
Digital Supply Voltage	VDD	3	3.3	3.6	V	SYSCLK > 50 MHz	39
Analog Supply Current			1.7		mA	Internal REF, ADCs, DACs, Comparators all active	39
Analog Supply Current with analog sub-systems inactive			0.2		µA	Internal REF, ADCs, DACs, Comparators all disabled, oscillator disabled	39
Analog-to-Digital Supply Delta (/VDD, AV+/)				0.5	V		39
Digital Supply Current with CPU active, 100 MHz			65		mA	VDD = 3.0 V, Clock = 100 MHz	39
Digital Supply Current with CPU active, 50 MHz			35		mA	VDD = 3.0 V, Clock = 50 MHz	39
Digital Supply Current with CPU inactive, 100 MHz			40		mA	VDD = 3.0 V, Clock = 100 MHz	39
Digital Supply Current (shutdown)			0.4		µA	Oscillator not running	39
Digital Supply RAM Data Retention Voltage			1.5		V		39
SYSCLK (System Clock)	SYSCLK	0		50	MHz	VDD, AV+ = 2.7 to 3.6 V	39
SYSCLK (System Clock)	SYSCLK	0		100	MHz	VDD, AV+ = 3.0 to 3.6 V	39
Specified Operating Temperature Range		-40		85	°C		39
Ambient temperature under bias		-55		125	°C		38
Storage Temperature		-65		150	°C		38
Voltage on any Pin (except VDD and Port I/O) with Respect to DGND		-0.3			V	Max is VDD + 0.3 V	38
Voltage on any Port I/O Pin or RST with Respect to DGND		-0.3		5.8	V		38
Voltage on VDD with Respect to DGND	VDD	-0.3		4.2	V		38
Maximum Total Current through VDD, AV+, DGND, and AGND				800	mA		38
Maximum Output Current Sunk by any Port pin				100	mA		38
Maximum Output Current Sunk by any other I/O pin				50	mA		38
Maximum Output Current Sourced by any Port pin				100	mA		38
Maximum Output Current Sourced by any other I/O Pin				50	mA		38
ADC0 Resolution			12		bits		72
ADC0 Integral Nonlinearity	INL	-1		1	LSB		72
ADC0 Differential Nonlinearity	DNL	-1		1	LSB	Guaranteed Monotonic	72
ADC0 Signal-to-Noise Plus Distortion	SINAD	66			dB	10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps	72
ADC0 SAR Clock Frequency				2.5	MHz		72
ADC0 Conversion Time in SAR Clocks		16			clocks		72
ADC0 Track/Hold Acquisition Time		1.5			µs		72
ADC0 Throughput Rate				100	ksps		72
ADC0 Power Supply Current (AV+ supplied to ADC)			450	900	µA	Operating Mode, 100 ksps	72
ADC2 Integral Nonlinearity	INL	-1		1	LSB		103
ADC2 Differential Nonlinearity	DNL	-1		1	LSB	Guaranteed Monotonic	103
ADC2 Signal-to-Noise Plus Distortion	SINAD	45	47		dB	10 kHz sine-wave input, 1 dB below Full Scale, 500 ksps	103
ADC2 SAR Clock Frequency				6	MHz		103
ADC2 Track/Hold Acquisition Time		300			ns		103
ADC2 Throughput Rate				500	ksps		103
ADC2 Power Supply Current (AV+ supplied to ADC2)			420	900	µA	Operating Mode, 500 ksps	103
DAC Differential Nonlinearity	DNL			1	LSB		111
DAC Offset Error			3	30	mV	Data Word = 0x014	111
DAC Full-Scale Error			20	60	mV		111
DAC Power Supply Current (AV+ supplied to DAC)			110	400	µA	Data Word = 0x7FF	111
Internal Reference Output Voltage	VREF	2.36	2.43	2.48	V	25 °C ambient	118
VREF Short-Circuit Current				30	mA		118
VREF Temperature Coefficient			15		ppm/°C		118
External Reference Input Voltage Range		1			V	REFBE = 0; max is (AV+), 0.3 V	118
External Reference Input Current			0	1	µA	REFBE = 0	118
Comparator Common-Mode Rejection Ratio			1.5	4	mV/V		126
Comparator Positive Hysteresis 2		2	4.5	7	mV	CPnHYP1-0 = 01	126
Comparator Positive Hysteresis 4		10	17	25	mV	CPnHYP1-0 = 11	126
Comparator Input Bias Current		-5	0.001	5	nA		126
Comparator Input Offset Voltage		-10		10	mV		126
RST Output Low Voltage				0.6	V	IOL = 8.5 mA, VDD = 2.7 to 3.6 V	183
VDD POR Threshold	VRST	2.4	2.55	2.7	V		183
Reset Time Delay		80	100	120	ms	RST rising edge after VDD crosses VRST threshold	183
Calibrated Internal Oscillator Frequency		24	24.5	25	MHz		185
PLL Output Frequency		25		100	MHz	Max operating frequency of C8051F124/5/6/7 is 50 MHz	195

CAD (KiCad official)

Symbol: C8051F121-GQR
Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: c8051f121-gqr-etched.step / c8051f121-gqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f121-gqr.step / c8051f121-gqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SILICON LABS datasheet (350 pp, sha256 24fdae17f6f8efe6, retrieved 2026-11-13, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

C8051F121-GQR

Verified C8051F121-GQR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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