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LMK03033CISQX

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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, WQFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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LMK03033CISQX

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · WQFN-48(7x7)

LMK03033CISQX from Texas Instruments, in a WQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin for the device; the datasheet lists it as Ground in Table 2-1.
2 Fout output Internal VCO frequency output, enabled only when the EN_Fout bit is set to 1 (default is disabled).
3 Vcc1 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
4 CLKuWire input MICROWIRE clock input for programming the control registers.
5 DATAuWire input MICROWIRE data input for programming the control registers.
6 LEuWire input MICROWIRE latch enable input for programming the control registers.
7 NC unconnected No connection; leave this pin unconnected.
8 Vcc2 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
9 LDObyp1 passive LDO bypass pin; connects to the LDO bypass network (paired with LDObyp2).
10 LDObyp2 passive LDO bypass pin; connects to the LDO bypass network (paired with LDObyp1).
11 GOE input Global output enable; when low, all clock outputs are disabled regardless of the individual CLKoutX_EN bits.
12 LD output Lock detect and test output; its mode is set by the PLL_MUX[3:0] register bits (default Hi-Z, disabled).
13 Vcc3 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
14 CLKout0 output LVDS clock output 0 (true).
15 CLKout0* output LVDS clock output 0 (complementary).
16 Vcc4 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
17 CLKout1 output LVDS clock output 1 (true).
18 CLKout1* output LVDS clock output 1 (complementary).
19 Vcc5 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
20 CLKout2 output LVDS clock output 2 (true).
21 CLKout2* output LVDS clock output 2 (complementary).
22 Vcc6 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
23 CLKout3 output Clock output 3 (true); LVDS for the LMK03033C, LVPECL for other parts in the family.
24 CLKout3* output Clock output 3 (complementary); LVDS for the LMK03033C, LVPECL for other parts in the family.
25 GND power_in Ground pin for the device; the datasheet lists it as Ground in Table 2-1.
26 Vcc7 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
27 SYNC* input Global clock output synchronization input (active low per the * suffix).
28 OSCin input Oscillator clock input; should be AC coupled.
29 OSCin* input Complementary oscillator clock input; should be AC coupled.
30 Vcc8 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
31 Vcc9 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
32 CPout output Charge pump output for the PLL loop filter.
33 Vcc10 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
34 NC unconnected No connection; leave this pin unconnected.
35 NC unconnected No connection; leave this pin unconnected.
36 Bias input Bias bypass pin for the internal bias circuitry; requires its bypass connection as described in the application section.
37 Vcc11 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
38 CLKout4 output LVPECL clock output 4 (true).
39 CLKout4* output LVPECL clock output 4 (complementary).
40 Vcc12 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
41 CLKout5 output LVPECL clock output 5 (true).
42 CLKout5* output LVPECL clock output 5 (complementary).
43 Vcc13 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
44 CLKout6 output LVPECL clock output 6 (true).
45 CLKout6* output LVPECL clock output 6 (complementary).
46 Vcc14 power_in Power supply pin; the device operates from 3.15 V to 3.45 V (3.3 V typical).
47 CLKout7 output LVPECL clock output 7 (true).
48 CLKout7* output LVPECL clock output 7 (complementary).
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48(7x7)
Category Clock/Timing
Pins 49

CAD (KiCad official)

  • Symbol: LMK03033CISQX
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: lmk03033cisqx-etched.step / lmk03033cisqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmk03033cisqx.step / lmk03033cisqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (48 pp, sha256 0cf7a425324a1ad2, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF