DP83TC814RRHARQ1 from Texas Instruments, in a VQFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MDC	input	Management data clock for MDIO serial management; maximum clock rate 20MHz with no minimum rate, and it may be asynchronous to the MAC clocks.
2	INT_N	output	Active-low interrupt output with a weak internal pull-up; it can alternatively be used as a power-down input, and the pin is powered from VDDIO.
3	RESET_N	input	Active-low reset input with an internal pull-up; it must be held low for at least 1µs to force a reset and straps are resampled on release.
4	XO	output	Crystal reference clock output used only with a crystal; it must be left floating when a CMOS-level oscillator drives XI.
5	XI	input	Reference clock input: 25MHz crystal or oscillator for MII/RGMII (50MHz CMOS oscillator in RMII slave mode), with a 100Ω series resistor when a crystal is used.
6	LED_1/GPIO_1	bidirectional	Link-status LED that flashes on TX/RX activity, selectable as an LED or clock output via strap/register; the pin is in the VDDIO voltage domain.
7	VDDA	power_in	Core supply pin at 3.3V (2.97V to 3.63V); a 0.1µF ceramic decoupling capacitor is recommended.
8	DNC	unconnected	Do not connect; leave floating.
9	NC	unconnected	No connect pin on this package; leave floating.
10	DNC	unconnected	Do not connect; leave floating.
11	VDDA	power_in	Core supply pin at 3.3V (2.97V to 3.63V); a 0.1µF ceramic decoupling capacitor is recommended.
12	TRD_P	bidirectional	Positive side of the 100BASE-T1 differential transmit and receive pair, which connects to the MDI through the coupling network with a 100Ω differential termination.
13	TRD_M	bidirectional	Negative side of the 100BASE-T1 differential transmit and receive pair, which connects to the MDI through the coupling network with a 100Ω differential termination.
14	RX_ER	output	Receive error output, synchronized to RX_CLK in MII mode and the reference clock in RMII mode; it is an RGMII input when the RGMII interface is selected.
15	RX_DV/CRS_DV/RX_CTRL	output	Multiplexed receive data valid (MII), carrier sense/data valid (RMII) or receive control (RGMII) output, selected by register 0x0551; it is in the VDDMAC domain.
16	CLKOUT/GPIO_2	bidirectional	25MHz reference clock output (50MHz in RMII slave mode), also selectable as LED or GPIO; the pin is in the VDDMAC domain.
17	GND_ESC	passive	Optional ground escape pin that may be connected to ground for PCB layout; it cannot replace the DAP power ground connection and may be left open if unused.
18	GND_ESC	passive	Optional ground escape pin that may be connected to ground for PCB layout; it cannot replace the DAP power ground connection and may be left open if unused.
19	DNC	unconnected	Do not connect; leave floating.
20	DNC	unconnected	Do not connect; leave floating.
21	NC	unconnected	No connect pin on this package; leave floating.
22	VDDMAC	power_in	Optional MAC interface supply at 1.8V, 2.5V or 3.3V that may differ from VDDIO; it must be tied to VDDIO when a separate rail is not needed.
23	RX_D3	output	Receive data bit 3 in MII/RGMII mode, RX_D[1:0] in RMII mode, and it outputs a 50MHz reference clock when RMII master mode is strapped; it is in the VDDMAC domain.
24	RX_D2	output	Receive data bit 2 for MII and RGMII modes, unused in RMII slave mode, and it is in the VDDMAC domain.
25	RX_D1	output	Receive data bit 1 for MII and RGMII modes and RMII receive data bit 1; it is in the VDDMAC domain.
26	RX_D0	output	Receive data bit 0 for all MAC modes; it is in the VDDMAC domain.
27	RX_CLK	output	Receive clock providing a 25MHz reference in MII and RGMII modes; it is not used in RMII mode.
28	TX_CLK	bidirectional	Transmit clock that is a 25MHz output in MII mode and is supplied by the MAC as an input in RGMII mode, requiring a 25MHz clock.
29	TX_EN/TX_CTRL	input	Transmit enable in MII/RMII modes or transmit control in RGMII mode, where TX_EN is sampled before the TX_CLK rising edge.
30	TX_D3	input	Transmit data bit 3 sampled before TX_CLK rising edge in MII and RGMII modes; unused in RMII slave mode.
31	TX_D2	input	Transmit data bit 2 sampled before TX_CLK rising edge in MII and RGMII modes; unused in RMII slave mode.
32	TX_D1	input	Transmit data bit 1 sampled before the TX_CLK (MII/RGMII) or reference clock (RMII) rising edge; it is in the VDDMAC domain.
33	TX_D0	input	Transmit data bit 0 sampled before the TX_CLK (MII/RGMII) or reference clock (RMII) rising edge; it is in the VDDMAC domain.
34	VDDIO	power_in	IO supply at 1.8V, 2.5V or 3.3V (1.62V to 3.63V); decoupling with ferrite bead, 0.47µF and 0.01µF ceramic capacitors is recommended.
35	LED_0/GPIO_0	bidirectional	Link status LED that can also be selected as an LED or clock output by register; it is in the VDDIO domain and has an internal pull-down.
36	MDIO	bidirectional	Bidirectional management data line that requires a pull-up to VDDIO (2.2kΩ to 9kΩ recommended), needed for MDIO/MDC access for Open Alliance compliance.
37	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-36(6x6)
Category	Communication Interface Chip/UART/485/232
Pins	37

CAD (KiCad official)

Symbol: DP83TC814RRHARQ1
Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
3D model: VQFN-36(6x6) (KiCad packages3D, STEP)
3D model files: dp83tc814rrharq1-etched.step / dp83tc814rrharq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83tc814rrharq1.step / dp83tc814rrharq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (161 pp, sha256 d1fe2a72e0f7d7e6, retrieved 2026-11-02, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DP83TC814RRHARQ1

Changed since verified DP83TC814RRHARQ1

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README

DP83TC814RRHARQ1

Pinout

Key specifications

CAD (KiCad official)

Provenance