component
AD5142ABCPZ10-RL7
Public Made by Adomby adom
Analog Devices Digital Potentiometers, LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownAD5142ABCPZ10-RL7
Analog Devices · Digital Potentiometers · LFCSP-16(3x3)
AD5142ABCPZ10-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin, logic ground reference. |
| 2 | A1 | passive | Terminal A of RDAC1, with VSS ≤ VA ≤ VDD. |
| 3 | W1 | passive | Wiper terminal of RDAC1, with VSS ≤ VW ≤ VDD. |
| 4 | B1 | passive | Terminal B of RDAC1, with VSS ≤ VB ≤ VDD. |
| 5 | VSS | power_in | Negative power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 6 | A2 | passive | Terminal A of RDAC2, with VSS ≤ VA ≤ VDD. |
| 7 | W2 | passive | Wiper terminal of RDAC2, with VSS ≤ VW ≤ VDD. |
| 8 | B2 | passive | Terminal B of RDAC2, with VSS ≤ VB ≤ VDD. |
| 9 | VDD | power_in | Positive power supply; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 10 | VLOGIC | power_in | Logic power supply, 1.8 V to VDD; decouple with 0.1 µF ceramic and 10 µF capacitors. |
| 11 | SCL | input | I2C serial clock line. |
| 12 | SDA | bidirectional | I2C serial data input/output. |
| 13 | ADDR1 | input | Programmable address pin (ADDR1) for multiple package decoding. |
| 14 | ADDR0 | input | Programmable address pin (ADDR0) for multiple package decoding. |
| 15 | INDEP | input | Selects linear gain setting mode at power-up; once enabled, it cannot be disabled by software. |
| 16 | RESET | input | Active-low hardware reset that refreshes the RDAC registers from EEPROM; tie to VLOGIC if not used. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| R-INL, VDD ≥ 2.7 V | R-INL | -2 | 0.2 | 2 | LSB | RAB = 10 kΩ; VDD ≥ 2.7 V | 5 |
| R-INL, VDD < 2.7 V | R-INL | -5 | 1.5 | 5 | LSB | RAB = 10 kΩ; VDD < 2.7 V | 5 |
| Resistor Differential Nonlinearity | R-DNL | -0.5 | 0.2 | 0.5 | LSB | 5 | |
| Nominal Resistor Tolerance | ΔRAB/RAB | -8 | 1 | 8 | % | 5 | |
| Wiper Resistance | RW | 55 | 125 | Ω | Code = zero scale; RAB = 10 kΩ | 5 | |
| Wiper Resistance, Bottom Scale or Top Scale | RBS or RTS | 40 | 80 | Ω | RAB = 10 kΩ | 5 | |
| Nominal Resistance Match | RAB1/RAB2 | -1 | 0.2 | 1 | % | Code = full scale | 5 |
| Integral Nonlinearity (potentiometer divider) | INL | -1 | 0.2 | 1 | LSB | RAB = 10 kΩ | 6 |
| Differential Nonlinearity (potentiometer divider) | DNL | -0.5 | 0.2 | 0.5 | LSB | 6 | |
| Full-Scale Error | VWFSE | -2.5 | -0.1 | LSB | RAB = 10 kΩ | 6 | |
| Zero-Scale Error | VWZSE | 1.2 | 3 | LSB | RAB = 10 kΩ | 6 | |
| Voltage Divider Temperature Coefficient | (ΔVW/VW)/ΔT × 10^6 | -5 | 5 | ppm/°C | Code = half scale | 6 | |
| Maximum Continuous Current IA, IB, IW | IA, IB, IW | -6 | 6 | mA | RAB = 10 kΩ | 6 | |
| Common-Mode Leakage Current | -500 | 15 | 500 | nA | VA = VW = VB | 6 | |
| Input Current | IIN | -1 | 1 | µA | 6 | ||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 3 mA | 6 | ||
| Output Low Voltage | VOL | 0.6 | V | ISINK = 6 mA, VLOGIC > 2.3 V | 6 | ||
| Three-State Leakage Current | -1 | 1 | µA | 6 | |||
| Single-Supply Power Range | VDD | 2.3 | 5.5 | V | VSS = GND | 6 | |
| Dual-Supply Power Range | VDD/VSS | 2.25 | 2.75 | V | Dual supply; printed as ±2.25 / ±2.75 V | 6 | |
| Logic Supply Range, single supply | VLOGIC | 1.8 | V | Single supply, VSS = GND; max printed as VDD | 6 | ||
| Logic Supply Range, dual supply | VLOGIC | 2.25 | V | Dual supply, VSS < GND; max printed as VDD | 6 | ||
| Positive Supply Current | IDD | 0.7 | 5.5 | µA | VIH = VLOGIC or VIL = GND; VDD = 5.5 V | 6 | |
| Positive Supply Current | IDD | 400 | nA | VIH = VLOGIC or VIL = GND; VDD = 2.3 V | 6 | ||
| Negative Supply Current | ISS | -5.5 | -0.7 | µA | VIH = VLOGIC or VIL = GND | 7 | |
| EEPROM Store Current | IDD_EEPROM_STORE | 2 | mA | VIH = VLOGIC or VIL = GND | 7 | ||
| EEPROM Read Current | IDD_EEPROM_READ | 320 | µA | VIH = VLOGIC or VIL = GND | 7 | ||
| Logic Supply Current | ILOGIC | 0.05 | 1.4 | µA | VIH = VLOGIC or VIL = GND | 7 | |
| Power Supply Rejection Ratio | PSRR | -66 | -60 | dB | ΔVDD/ΔVSS = VDD ± 10%, code = full scale | 7 | |
| VDD to GND | -0.3 | 7 | V | 10 | |||
| VSS to GND | -7 | 0.3 | V | 10 | |||
| VDD to VSS | 7 | V | 10 | ||||
| VLOGIC to GND | -0.3 | 7 | V | Max: VDD + 0.3 V or +7.0 V, whichever is less | 10 | ||
| VA, VW, VB to GND | 7 | V | Max: VDD + 0.3 V or +7.0 V, whichever is less | 10 | |||
| Terminal current IA, IW, IB, pulsed, frequency > 10 kHz | IA, IW, IB | -6 | 6 | mA/d | RAB = 10 kΩ; pulsed; d = pulse duty factor | 10 | |
| Terminal current IA, IW, IB, pulsed, frequency ≤ 10 kHz | IA, IW, IB | -6 | 6 | mA/√d | RAB = 10 kΩ; pulsed; d = pulse duty factor | 10 | |
| Digital Inputs voltage | -0.3 | 7 | V | Max: VLOGIC + 0.3 V or +7 V, whichever is less | 10 | ||
| Operating Temperature Range, TA | TA | -40 | 125 | °C | Includes programming of EEPROM memory | 10 | |
| Maximum Junction Temperature | TJ | 150 | °C | 10 | |||
| Storage Temperature Range | -65 | 150 | °C | 10 | |||
| Reflow Soldering Peak Temperature | 260 | °C | 10 | ||||
| Time at Reflow Peak Temperature | 20 | 40 | sec | 10 | |||
| Resistance Temperature Coefficient | (ΔRAB/RAB)/ΔT × 10^6 | 35 | ppm/°C | Code = full scale | 5 | ||
| Nominal Resistance (RAB) | RAB | 10 | kΩ | Model AD5142ABCPZ10-RL7 per ordering guide | 28 | ||
| Thermal Resistance, junction to ambient, 16-Lead LFCSP | θJA | 75.4 | °C/W | JEDEC natural convection, 2S2P test board | 10 | ||
| Thermal Resistance, junction to board, 16-Lead LFCSP | θJB | 33.4 | °C/W | JEDEC θJB environment | 10 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | EPAD Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plan | 11 |
CAD (KiCad official)
- Symbol:
AD5142ABCPZ10-RL7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
ad5142abcpz10-rl7-etched.step/ad5142abcpz10-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5142abcpz10-rl7.step/ad5142abcpz10-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (29 pp, sha256
d67bcce85b5eaa84, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).