component
CY8C4046LQI-T452
Public Made by Adomby adom
Infineon/Cypress Semicon , QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCY8C4046LQI-T452
Infineon/Cypress Semicon · IC · QFN-24(4x4)
CY8C4046LQI-T452 from Infineon/Cypress Semicon, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P2.1 | bidirectional | GPIO port 2 bit 1 with CAPSENSE sense/drive function csd.msc_gpio_ctrl_sns[8] and Deep Sleep csd.obs_data[2]. |
| 2 | P2.2 | bidirectional | GPIO port 2 bit 2 with CAPSENSE sense function, tcpwm.line[0]:1, uart_rx:3, spi_mosi:3 and scb[1].i2c_scl:1 alternates. |
| 3 | P2.3 | bidirectional | GPIO port 2 bit 3 with CAPSENSE sense function, tcpwm.line_compl[0]:1, uart_tx:3, spi_miso:3 and scb[1].i2c_sda:1 alternates. |
| 4 | P2.4 | bidirectional | GPIO port 2 bit 4 with CAPSENSE sense function, tcpwm.line[1]:1, uart_cts:3, spi_clk:3 and csd.ext_sync:1 alternates. |
| 5 | P2.5 | bidirectional | GPIO port 2 bit 5 with CAPSENSE sense function, tcpwm.line_compl[1]:1, uart_rts:3, spi_select0:3 and csd.ext_sync_clk:1 alternates. |
| 6 | P3.0 | bidirectional | GPIO port 3 bit 0 with CAPSENSE sense function, tcpwm.line[0]:0, uart_rx:1, i2c_scl:1 and spi_mosi:1 alternates. |
| 7 | P3.2 | bidirectional | GPIO port 3 bit 2 with CAPSENSE sense function, tcpwm.line[1]:0, uart_cts:1, spi_clk:1, scb[1].i2c_sda:0 and SWD data (cpuss.swd_data:0) alternates. |
| 8 | P3.3 | bidirectional | GPIO port 3 bit 3 with CAPSENSE sense function, tcpwm.line_compl[1]:0, uart_rts:1, spi_select0:1, scb[1].i2c_scl:0 and SWD clock (cpuss.swd_clk:0) alternates. |
| 9 | P4.0 | bidirectional | GPIO port 4 bit 0 with CAPSENSE sense function, uart_rx:0, i2c_scl:0, spi_mosi:2 and tcpwm.tr_in[6] alternates. |
| 10 | P4.1 | bidirectional | GPIO port 4 bit 1 with CAPSENSE sense function, uart_tx:0, i2c_sda:0 and spi_miso:2 alternates. |
| 11 | P4.2 | bidirectional | GPIO port 4 bit 2 with CAPSENSE Cmod1 function (csd.msc_gpio_ctrl_cmod1), uart_cts:0 and spi_clk:2 alternates. |
| 12 | P4.3 | bidirectional | GPIO port 4 bit 3 with CAPSENSE Cmod2 function (csd.msc_gpio_ctrl_cmod2), uart_rts:0 and spi_select0:2 alternates. |
| 13 | P0.0 | bidirectional | GPIO port 0 bit 0 with CAPSENSE sense function, tcpwm.tr_in[0], csd.ext_sync:0 and spi_select1:0 alternates. |
| 14 | P0.1 | bidirectional | GPIO port 0 bit 1 with CAPSENSE sense function, tcpwm.tr_in[1], csd.ext_sync_clk:0 and spi_select2:0 alternates. |
| 15 | P0.2 | bidirectional | GPIO port 0 bit 2 with CAPSENSE sense function, uart_rx:2, i2c_scl:2, spi_mosi:0 and SWD clock (cpuss.swd_clk:1) alternates. |
| 16 | P0.3 | bidirectional | GPIO port 0 bit 3 with CAPSENSE sense function, uart_tx:2, i2c_sda:2, spi_miso:0 and SWD data (cpuss.swd_data:1) alternates. |
| 17 | P0.4 | bidirectional | GPIO port 0 bit 4 with CAPSENSE sense function, srss.ext_clk, uart_cts:2, spi_clk:0 and csd.ext_frm_start:0 alternates. |
| 18 | XRES | input | External reset input for the device. |
| 19 | VCCD | power_out | Regulated digital supply (1.8 V ±5%); must be bypassed to ground with a 2.2 µF X5R ceramic or better capacitor and connected to nothing else in the 2.0 V to 5.5 V supply mode, or shorted to VDDD in the 1.8 V ±5% supply mode. |
| 20 | VSSD | power_in | Ground pin for the digital section. |
| 21 | VDDD | power_in | Power supply for the digital section, 2.0 V to 5.5 V (or 1.71 V to 1.89 V when externally regulated). |
| 22 | VSSA | power_in | Ground pin for the CAPSENSE section. |
| 23 | P1.0 | bidirectional | GPIO port 1 bit 0 with CAPSENSE sense function, tcpwm.line[1]:2, tcpwm.tr_in[2] and spi_select3:0 alternates. |
| 24 | P2.0 | bidirectional | GPIO port 2 bit 0 with CAPSENSE sense function, tcpwm.line_compl[1]:2, tcpwm.tr_in[3] and csd.obs_data[3] alternates. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon/Cypress Semicon |
| Package | QFN-24(4x4) |
| Category | |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog or digital supply relative to VSS | VDD_ABS | -0.5 | 6 | V | Absolute maximum | 18 | |
| Direct digital core voltage input relative to VSSD | VCCD_ABS | -0.5 | 1.95 | V | Absolute maximum | 18 | |
| GPIO voltage | VGPIO_ABS | -0.5 | V | Absolute maximum; max printed as VDDD+0.5 | 18 | ||
| Current per GPIO | IGPIO_ABS | -25 | 25 | mA | Absolute maximum | 18 | |
| GPIO injection current per pin | IGPIO_injection | -0.5 | 0.5 | mA | Absolute maximum | 18 | |
| ESD voltage HBM | ESD_HBM | -2 | 2 | kV | Human Body Model per ANSI/ESDA/JEDEC JS-001 | 18 | |
| ESD voltage CDM | ESD_CDM | -1 | 1 | kV | Charged Device Model per ANSI/ESDA/JEDEC JS-002 | 18 | |
| Latch-up current limits | I_LU | -100 | 100 | mA | Max/min current into any input or output, pin-to-pin, pin-to-supply at 125°C ambient | 18 | |
| Power supply input voltage | VDDD | 2 | 5.5 | V | With internal regulator enabled | 18 | |
| Power supply input voltage | VDDD | 1.71 | 1.8 | 1.89 | V | Internal regulator enabled; VCCD connected to VDDD | 18 |
| Power supply decoupling capacitor tolerance | CEXC | -30 | 30 | % | X5R ceramic or better; typ 4.7 µF | 18 | |
| Active current, CPU at 6 MHz | IDD5 | 1.8 | 2.7 | mA | Execute from flash; Typ = 25°C @ VDDD = 3.3 V, Max = 85°C @ 5.5 V | 18 | |
| Active current, CPU at 24 MHz | IDD11 | 3 | 4.8 | mA | Execute from flash; Typ = 25°C @ VDDD= 3.3 V, Max = 85°C @ 5.5 V | 18 | |
| Active current, CPU at 48 MHz | IDD14 | 5.4 | 6.9 | mA | Execute from flash; Typ = 25°C @ VDDD= 3.3V, Max = 85°C @ 5.5 V | 18 | |
| Sleep current, 6 MHz, VDDD 2.0 to 5.5 V | IDD17 | 1.7 | 2.2 | mA | I2C wakeup, WDT, and comparators on; Typ = 25°C @ VDDD = 3.3 V, Max = 85°C @ 5.5 V | 18 | |
| Sleep current, 6 MHz, VDDD 1.71 to 1.89 V | IDD23 | 1.7 | 2.2 | mA | I2C wakeup, WDT, and comparators on; Typ = 25°C @ VDDD = 1.8 V, Max = 85°C @ 1.89 V | 19 | |
| Deep Sleep current, VDDD 2.0 to 3.6 V | IDD26 | 2.5 | 60 | µA | I2C wakeup and WDT on; Typ = 25°C @ VDDD = 3.3 V, Max = 85°C @ 3.6 V | 19 | |
| Deep Sleep current, VDDD 3.6 to 5.5 V | IDD29 | 2.5 | 60 | µA | I2C wakeup and WDT on; Typ = 25°C @ VDDD= 3.3 V, Max = 85°C @ 5.5 V | 19 | |
| Deep Sleep current, VDDD 1.71 to 1.89 V | IDD32 | 2.5 | 65 | µA | I2C wakeup and WDT on; Typ = 25°C @ VDDD = 1.8 V, Max = 85°C @ 1.89 V | 19 | |
| Supply current while XRES asserted | IDD_XR | 2 | 5 | mA | 19 | ||
| CPU frequency | FCPU | 48 | MHz | 1.71 VDDD 5.5; min printed as DC | 19 | ||
| Wakeup from Deep Sleep mode | TDEEPSLEEP | 25 | 30 | µs | 19 | ||
| XRES input capacitance | CIN | 7 | pF | 21 | |||
| XRES protection diode current | IDIODE | 100 | µA | Current through protection diode to VDDD/VSS | 21 | ||
| XRES reset pulse width | TRESETWIDTH | 1 | µs | 21 | |||
| Wake-up time from reset release | TRESETWAKE | 2.7 | ms | 21 | |||
| Max allowed ripple on power supply, 1 kHz to 10 MHz | VDD_RIPPLE | -50 | 50 | mV | VDDD ≥ 2 V (with ripple), 25°C TA, Sensitivity ≥ 50 counts/0.1 pF, 2 pF < Cs < 50 pF | 22 | |
| Max allowed ripple on power supply, 1 kHz to 10 MHz | VDD_RIPPLE_1.8 | -25 | 25 | mV | VDDD ≥ 1.75 V (with ripple), 25°C TA, sensitivity ≥ 50 counts / 0.1 µH, 0.1 µH < Lx < 150 µH | 22 | |
| Modulator frequency | FMOD | 46 | MHz | All VDDD | 22 | ||
| MSCLP clock frequency variation at 25 MHz, 38MHz, and 46 MHz | FMSCLP_IMO_TOL | -2 | 2.5 | % | All VDDD | 22 | |
| Voltage range of operation | VMSC_LP | 1.71 | 5.5 | V | 1.8 V ±5% externally regulated, 2 V to 5.5 V externally unregulated | 22 | |
| CMOD accuracy | CMOD accuracy | -5 | 5 | % | Required tolerance on CMOD capacitance value | 22 | |
| CAPSENSE SNR | SNR | 5 | Ratio | Capacitance range of 5 to 50 pF, sensitivity ≥ 50 counts / 0.1 pF, VDDA ≥ 2 V | 23 | ||
| Capacitive sense frequency range | FCAPSENSE | 45 | 6000 | kHz | 23 | ||
| Input capacitance range for self-capacitance | CIN_Self | 2 | 200 | pF | 23 | ||
| Input capacitance range for mutual capacitance | CIN_Mutual | 0.5 | 30 | pF | 23 | ||
| Supported sensor inductance range | LX | 0.1 | 200 | µH | 24 | ||
| Inductive sensing SNR | SNR | 5 | Ratio | LX range of 1 to 150 µH, sensitivity ≥ 50 counts / 0.1 µH, VDDA ≥ 2 V | 24 | ||
| Sensor excitation frequency | FLX | 40 | 5700 | kHz | 24 | ||
| Refresh rate | Refresh rate | 2500 | sps | 1 sensors, 200 µs scan time | 24 | ||
| Proximity detection range | RLPROX | 50 | 100 | % dOUT | % of diameter/ diagonal of the sensor | 24 | |
| Scan initialization time after power on | TINIT | 0.1 | 0.5 | 10 | ms | 24 | |
| SWDCLK frequency, 3.3 V ≤ VDDD ≤ 5.5 V | F_SWDCLK1 | 14 | MHz | SWDCLK ≤ 1/3 FCPU | 29 | ||
| SWDCLK frequency, 1.71 V ≤ VDDD ≤ 3.3 V | F_SWDCLK2 | 7 | MHz | SWDCLK ≤ 1/3 FCPU | 29 | ||
| SWDO hold time | T_SWDO_HOLD | 1 | ns | T = 1/f SWDCLK | 29 | ||
| IMO operating current at 48 MHz | IIMO1 | 250 | µA | 29 | |||
| IMO frequency variation at 24, 32, and 48 MHz (trimmed) | FIMOTOL1 | -2 | 2 | % | 29 | ||
| IMO startup time | TSTARTIMO | 7 | µs | 29 | |||
| ILO operating current at 32 KHz | IILO2 | 0.3 | 1.05 | µA | 29 | ||
| ILO startup time | TSTARTILO1 | 2 | ms | 29 | |||
| ILO duty cycle | TILODUTY | 40 | 50 | 60 | % | 29 | |
| ILO frequency range | FILOTRIM1 | 20 | 40 | 80 | kHz | 29 | |
| Operating ambient temperature | TA | -40 | 25 | 105 | °C | Package thermal characteristics table; ordering table lists -40 to 85 for this MPN | 35 |
| Operating junction temperature | TJ | -40 | 25 | 125 | °C | 35 | |
| Package θJA | TJA | 20.53 | °C/Watt | QFN 24 (0.5 mm pitch) | 35 | ||
| Package θJC | TJC | 18.26 | °C/Watt | QFN 24 (0.5 mm pitch) | 35 | ||
| Pull-up resistor | RPULLUP | 60 | kΩ | 21 | |||
| Input voltage hysteresis | VHYSXRES | 100 | mV | 21 | |||
| External modulator capacitor | CMOD | 2.2 | nF | 5 V rating | 22 |
CAD (KiCad official)
- Symbol:
CY8C4046LQI-T452 - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
cy8c4046lqi-t452-etched.step/cy8c4046lqi-t452-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy8c4046lqi-t452.step/cy8c4046lqi-t452.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon/Cypress Semicon datasheet (46 pp, sha256
91700ca10102b80f, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).