component
MP2797DFP-0000-T
Public Made by Adomby adom
Monolithic Power Systems Inc. Others, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownMP2797DFP-0000-T
Monolithic Power Systems Inc. · Others · TQFP-48(7x7)
MP2797DFP-0000-T from Monolithic Power Systems Inc., in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | C13 | input | Connect to the positive pin of cell 13; if fewer than 16 cells are used, unused cell channels connect to the practical maximum cell channel. |
| 2 | C12 | input | Connect to the positive pin of cell 12; if fewer than 16 cells are used, unused cell channels connect to the practical maximum cell channel. |
| 3 | C11 | input | Connect to the positive pin of cell 11; if fewer than 16 cells are used, unused cell channels connect to the practical maximum cell channel. |
| 4 | C10 | input | Connect to the positive pin of cell 10; if fewer than 16 cells are used, unused cell channels connect to the practical maximum cell channel. |
| 5 | C9 | input | Connect to the positive pin of cell 9; if fewer than 16 cells are used, unused cell channels connect to the practical maximum cell channel. |
| 6 | C8 | input | Connect to the positive pin of cell 8; if fewer than 16 cells are used, unused cell channels connect to the practical maximum cell channel. |
| 7 | C7 | input | Connect to the positive pin of cell 7. |
| 8 | C6 | input | Connect to the positive pin of cell 6. |
| 9 | C5 | input | Connect to the positive pin of cell 5. |
| 10 | C4 | input | Connect to the positive pin of cell 4. |
| 11 | C3 | input | Connect to the positive pin of cell 3. |
| 12 | C2 | input | Connect to the positive pin of cell 2. |
| 13 | C1 | input | Connect to the positive pin of cell 1. |
| 14 | C0 | input | Connect to the negative pin of cell 1; recommended C0 to AGND range is -0.25V to +0.3V. |
| 15 | SRP | input | Positive current-sense pin; SRP to SRN is limited to -100mV to +100mV, and SRP/SRN should be connected to AGND if current sensing is not used. |
| 16 | SRN | input | Negative current-sense pin; SRP to SRN is limited to -100mV to +100mV, and SRP/SRN should be connected to AGND if current sensing is not used. |
| 17 | NTC4 | input | Thermistor 4 terminal; float this pin if the NTC channel is unused. |
| 18 | NTC3 | input | Thermistor 3 terminal; float this pin if the NTC channel is unused. |
| 19 | NTC2 | input | Thermistor 2 terminal; float this pin if the NTC channel is unused. |
| 20 | NTC1 | input | Thermistor 1 terminal; float this pin if the NTC channel is unused. |
| 21 | NTCB | output | NTC bias output; float this pin if NTC temperature monitoring is not used. |
| 22 | VREF | power_in | ADC reference voltage. |
| 23 | AGND | power_in | Ground; connect AGND near the positive connection (SRP) of the low-side sense resistor. |
| 24 | REGCTRL | power_in | Turn-on control for the external BJT low-dropout (LDO) regulator; REGCTRL to AGND is rated -0.3V to +15V. |
| 25 | REGIN | power_in | Internal regulator input; connect an external 3.3μF bypass capacitor from REGIN to AGND, with REGIN voltage specified at 4.5V to 5.5V. |
| 26 | 3V3 | power_out | 3.3V voltage output to drive external peripherals; bypass with an external 1µF capacitor. |
| 27 | VDD | power_out | 1.8V rail for internal use; connect a 1μF bypass capacitor from VDD to AGND (VDD to AGND is rated -0.3V to +2V). |
| 28 | xALERT | output | Interrupt alert output; float this pin if it is not used. |
| 29 | WDT | bidirectional | Watchdog timer pin; float this pin if it is not used. |
| 30 | NSHDN | input | Active-low shutdown input signal; NSHDN to AGND is rated -0.3V to +9V. |
| 31 | SCL/SCK | input | Multi-function pin that can be set as the I2C interface clock or the SPI interface clock. |
| 32 | SDA/SDI | bidirectional | Multi-function pin that can be set as the I2C interface data or the SPI serial data input. |
| 33 | SDO | output | SPI serial data output; float this pin if it is not used. |
| 34 | GPIO3/nCS | bidirectional | Multi-function pin that can be set as GPIO3 or as the SPI chip select; float if unused, and set to 20kΩ pull-up mode via GPIO_CFG to avoid extra power consumption. |
| 35 | GPIO2 | bidirectional | General-purpose pin 2; float if unused and set to 20kΩ pull-up mode via GPIO_CFG to avoid extra power consumption. |
| 36 | GPIO1 | bidirectional | General-purpose pin 1; float if unused and set to 20kΩ pull-up mode via GPIO_CFG to avoid extra power consumption. |
| 37 | GPIOHV1 | bidirectional | General-purpose, high-voltage pin 1; GPIOHV1 to AGND is rated -0.3V to +86V and GPIOHV1 to VTOP is rated +0.3V max. |
| 38 | PACKP | bidirectional | Pack sensing voltage (load side); PACKP to AGND is rated -0.5V to +86V. |
| 39 | DSG | output | Discharge MOSFET driver; DSG to AGND is rated -0.3V to +100V. |
| 40 | N/C | unconnected | Not connected. |
| 41 | SBYDSG | output | Discharge bypass P-channel MOSFET driver; SBYDSG to AGND is rated -0.3V to +86V. |
| 42 | VCP | power_out | Charge pump regulated voltage; connect a 47nF capacitor from VCP to VMID and adjust the value based on the number of parallel DSG and CHG MOSFETs. |
| 43 | VMID | power_out | Protection MOSFET middle point; VMID to AGND is rated -0.3V to +86V. |
| 44 | CHG | output | Charge MOSFET driver; CHG to AGND is rated -0.3V to +100V. |
| 45 | VTOP | power_in | Battery-side pack-sensing voltage and low-current positive supply; VTOP must connect to the top of the battery stack, and VTOP to AGND is rated -0.3V to +86V (recommended supply 18V to 75.2V). |
| 46 | C16 | input | Connect to the positive pin of cell 16. |
| 47 | C15 | input | Connect to the positive pin of cell 15. |
| 48 | C14 | input | Connect to the positive pin of cell 14. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Monolithic Power Systems Inc. |
| Package | TQFP-48(7x7) |
| Category | Others |
| Pins | 48 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| CHG, DSG, VCP to AGND | -0.3 | 100 | V | 7 | |||
| SBYDSG to AGND | -0.3 | 86 | V | 7 | |||
| GPIOHV1 to AGND | -0.3 | 86 | V | 7 | |||
| GPIOHV1 to VTOP | 0.3 | V | 7 | ||||
| VTOP to AGND | -0.3 | 86 | V | 7 | |||
| PACKP to AGND | -0.5 | 86 | V | 7 | |||
| VMID to AGND | -0.3 | 86 | V | 7 | |||
| Cx - C(x-1) | -0.3 | 10 | V | x: 1 to 16 | 7 | ||
| C16 to AGND | -0.3 | 86 | V | 7 | |||
| Cx to AGND | -0.3 | V | x: 1 to 15; upper limit printed as (n - 1) x 5.375 +7V, not evaluated | 7 | |||
| C0 to AGND | -0.5 | 5.7 | V | 7 | |||
| SRP, SRN to AGND | -0.5 | 6 | V | 7 | |||
| VCP to VMID | -0.3 | 20 | V | 7 | |||
| REGCTRL to AGND | -0.3 | 15 | V | 7 | |||
| NSHDN to AGND | -0.3 | 9 | V | 7 | |||
| VDD to AGND | -0.3 | 2 | V | 7 | |||
| All other pins to AGND | -0.3 | 6 | V | 7 | |||
| Junction temperature | 150 | °C | 7 | ||||
| Storage temperature | -65 | 150 | °C | 7 | |||
| ESD Human body model (HBM) | 1.5 | kV | Tested per ANSI/ESDA/JEDEC JS-001 | 7 | |||
| ESD Charged device model (CDM) | 500 | V | Tested per ANSI/ESDA/JEDEC JS-002 | 7 | |||
| VTOP voltage | 18 | 75.2 | V | 7 | |||
| Cx - C(x-1) | 1 | 5 | V | x: 1 to 16; stack voltage should exceed 18V | 7 | ||
| C0 to AGND | -0.25 | 0.3 | V | 7 | |||
| Operating temperature (TJ) | -40 | 85 | °C | 7 | |||
| SRP to SRN | -100 | 100 | mV | 7 | |||
| Cell leakage | ICx_LEAK | -200 | 200 | nA | TA = 25°C | 8 | |
| Cell leakage | ICx_LEAK | -600 | 600 | nA | TA = -40°C to +85°C | 8 | |
| Supported cell number | NCELL | 7 | 16 | Guaranteed by design (note 7) | 8 | ||
| VTOP supply voltage range | VVTOP_SUPPLY | 18 | 75.2 | V | TA = -40°C to +85°C | 8 | |
| VTOP under-voltage lockout (UVLO) threshold | VVTOP_UVLO | 14.6 | 15.8 | 17 | V | Falling edge, TA = -40°C to +85°C | 8 |
| VTOP under-voltage (UV) hysteresis | VVTOP_UVLO_HYST | 0.78 | 1.5 | V | TA = -40°C to +85°C | 8 | |
| Current ADC measurement range | VSRPN | -100 | 100 | mV | TA = -40°C to +85°C | 8 | |
| Current ADC measurement gain error | IADC_GAIN_ERR | -0.5 | 0.5 | % | 16-bit conversion, FSR = 100mV, SRP-N common mode +300mV to -125mV from GND, TA = 25°C | 8 | |
| Current ADC measurement gain error | IADC_GAIN_ERR | -1 | 1 | % | 16-bit conversion, FSR = 100mV, SRP-N common mode +300mV to -125mV from GND, TA = -40°C to 85°C | 8 | |
| Current-sense offset | VIADC_ACC_OFFSET | -12 | 12 | µV | SRP - SRN = 0V, SRP-N common mode +300mV to -125mV from GND, TA = -40°C to +85°C | 9 | |
| Total cell measurement error | VCELL_ERR | -5 | 5 | mV | VCELL = 2V to 4.5V, TA = 25°C | 9 | |
| Total cell measurement error | VCELL_ERR | -12.5 | 12.5 | mV | VCELL = 2V to 4.5V, TA = -40°C to +85°C | 9 | |
| Total cell measurement error | VCELL_ERR | -15 | 15 | mV | VCELL = 1V to 5V, TA = -40°C to +85°C | 9 | |
| Cell ADC measurement range | VCELL | 1 | 5 | V | TA = -40°C to +85°C | 9 | |
| Die temperature operating range | TDIE | -40 | 85 | °C | 9 | ||
| Over-temperature (OT) analog shutdown threshold | TDIE_OTSD | 140 | 155 | °C | 9 | ||
| VTOP total measurement error | VVTOP_ERR | -250 | 250 | mV | 15-bit conversion (positive range), TA = -40°C to +85°C | 10 | |
| Pack measurement range | VPACKP | 2.5 | 75.2 | V | TA = -40°C to +85°C | 10 | |
| Pack total measurement error | VPACKP_ERR | -250 | 250 | mV | 15-bit conversion (positive range), TA = -40°C to +85°C | 10 | |
| REGCTRL output voltage | VREGCTRL | 5.45 | 5.6 | 5.75 | V | VTOP = 18V to 75.2V, REGCTRL load current = 0mA and 1mA, TA = -40°C to +85°C | 13 |
| REGIN voltage | VREGIN | 4.65 | 5.1 | 5.4 | V | With external REGIN BJT_FZT853TA, VTOP = 18V to 75.2V, load current 1mA and 50mA, TA = -40°C to +85°C | 13 |
| REGIN analog UV | VREGIN_UV | 4.16 | 4.3 | 4.44 | V | External power to REGIN, falling edge, VTOP = 18V to 75.2V, TA = -40°C to +85°C | 13 |
| 3V3 output accuracy | V3V3_ACC | -5 | 5 | % | TA = -40°C to +85°C | 13 | |
| 3V3 short-circuit current | I3V3_EFET | 55 | 68 | 80 | mA | External power to REGIN, TA = -40°C to +85°C | 13 |
| CHG gate drive voltage accuracy | VCHG_ACC | 9.3 | 10.7 | V | CLOAD = 80nF, VTOP = 18V to 75.2V, 10V selected, TA = -40°C to +85°C | 14 | |
| DSG gate driver voltage accuracy | VDSG_ACC | 9.3 | 10.7 | V | CLOAD = 80nF, VTOP = 18V to 75.2V, 10V selected, TA = -40°C to +85°C | 15 | |
| On-resistance for the balancing MOSFET | RDS(ON)_BAL_FET | 15 | 50 | Ω | TA = -40°C to +85°C | 13 | |
| Internal clock frequency | f2M_CLOCK | 1.85 | 2 | 2.15 | MHz | VTOP = 18V to 75.2V, TA = -40°C to +85°C | 16 |
| Low-frequency internal clock | f32K_CLOCK | 31.2 | 32 | 32.8 | kHz | VTOP = 18V to 75.2V, TA = 25°C | 16 |
| Thermal resistance, junction-to-ambient | RθJA | 46.6 | °C/W | Metrics per EIA/JESD51-2, 7, and 8 setup conditions | 7 | ||
| Thermal resistance, junction-to-case (top) | RθJC(TOP) | 14.5 | °C/W | Metrics per EIA/JESD51-2, 7, and 8 setup conditions | 7 | ||
| Thermal resistance, junction-to-board (top) | RθJB(TOP) | 27.1 | °C/W | Metrics per EIA/JESD51-2, 7, and 8 setup conditions | 7 |
CAD (KiCad official)
- Symbol:
MP2797DFP-0000-T - Footprint:
Package_QFP:TQFP-48_7x7mm_P0.5mm - 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
mp2797dfp-0000-t-etched.step/mp2797dfp-0000-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp2797dfp-0000-t.step/mp2797dfp-0000-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Monolithic Power Systems Inc. datasheet (130 pp, sha256
725d60e60c57fa43, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).