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SN65LVDT32BDR

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Texas Instruments LVDS ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN65LVDT32BDR

Texas Instruments · LVDS ICs · SOIC-16

SN65LVDT32BDR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1B input Channel 1 bus input B; the differential input is defined as VID = VA − VB, so B is the inverting input, with VI or VIC limited to −2 V to 4.4 V.
2 1A input Channel 1 bus input A; the differential input is defined as VID = VA − VB, so A is the non-inverting input, with VI or VIC limited to −2 V to 4.4 V.
3 1Y output Channel 1 receiver output, with VOH of at least 2.4 V at IOH = −4 mA and VOL of at most 0.4 V at IOL = 4 mA.
4 G input Shared receiver enable for all four channels; VIH is at least 2 V and VIL is at most 0.8 V, and the datasheet's overbar polarity is lost in this extraction.
5 2Y output Channel 2 receiver output, with VOH of at least 2.4 V at IOH = −4 mA and VOL of at most 0.4 V at IOL = 4 mA.
6 2A input Channel 2 bus input A; the differential input is defined as VID = VA − VB, so A is the non-inverting input, with VI or VIC limited to −2 V to 4.4 V.
7 2B input Channel 2 bus input B; the differential input is defined as VID = VA − VB, so B is the inverting input, with VI or VIC limited to −2 V to 4.4 V.
8 GND power_in Device ground; all voltages are referenced to the network ground terminal.
9 3B input Channel 3 bus input B; the differential input is defined as VID = VA − VB, so B is the inverting input, with VI or VIC limited to −2 V to 4.4 V.
10 3A input Channel 3 bus input A; the differential input is defined as VID = VA − VB, so A is the non-inverting input, with VI or VIC limited to −2 V to 4.4 V.
11 3Y output Channel 3 receiver output, with VOH of at least 2.4 V at IOH = −4 mA and VOL of at most 0.4 V at IOL = 4 mA.
12 G input Shared receiver enable for all four channels; VIH is at least 2 V and VIL is at most 0.8 V, and the datasheet's overbar polarity is lost in this extraction.
13 4Y output Channel 4 receiver output, with VOH of at least 2.4 V at IOH = −4 mA and VOL of at most 0.4 V at IOL = 4 mA.
14 4A input Channel 4 bus input A; the differential input is defined as VID = VA − VB, so A is the non-inverting input, with VI or VIC limited to −2 V to 4.4 V.
15 4B input Channel 4 bus input B; the differential input is defined as VID = VA − VB, so B is the inverting input, with VI or VIC limited to −2 V to 4.4 V.
16 VCC power_in Supply voltage of 3 V to 3.6 V (3.3 V nominal); absolute maximum rating is −0.5 V to 4 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: SN65LVDT32BDR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn65lvdt32bdr-etched.step / sn65lvdt32bdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvdt32bdr.step / sn65lvdt32bdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 a6fe6aaf7a83af37, retrieved 2026-10-10, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF