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AD7658YSTZ-1

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Analog Devices Analog To Digital Converters (ADCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7658YSTZ-1

Analog Devices · Analog To Digital Converters (ADCs) · LQFP-64(10x10)

AD7658YSTZ-1 from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DB14/REFBUFEN/DIS bidirectional Parallel data bit 14 in parallel mode; in serial mode it enables or disables the internal reference buffers.
2 DB13 bidirectional Parallel data bit 13 used to output the conversion result or write the control register; tie to DGND in serial mode.
3 DB12 bidirectional Parallel data bit 12 used to output the conversion result or write the control register; tie to DGND in serial mode.
4 DB11 tri_state Parallel data bit 11 three-state output; tie to DGND when the serial interface is selected.
5 DB10/DOUT C tri_state Parallel data bit 10 in parallel mode; serial data output C for serial mode when SEL C = 1.
6 DB9/DOUT B tri_state Parallel data bit 9 in parallel mode; serial data output B for serial mode when SEL B = 1.
7 DB8/DOUT A tri_state Parallel data bit 8 in parallel mode; serial data output A for serial mode when SEL A = 1.
8 DGND power_in Digital ground reference for all digital circuitry; must be within 0.3 V of AGND even on a transient basis.
9 VDRIVE power_in Logic power supply input that sets the operating voltage of the interface, nominally the host interface supply, specified 2.7 V to 5.25 V.
10 DB7/HBEN/DCEN bidirectional Parallel data bit 7 in word mode, HBEN in byte mode, and DCEN enabling daisy-chain mode in serial mode; tie to DGND when not used in daisy-chain.
11 DB6/SCLK input Parallel data bit 6 in parallel mode; serial read clock input SCLK in serial mode.
12 DB5/DCIN A input Parallel data bit 5 in parallel mode; daisy-chain input A when SER/PAR SEL = 1 and DCEN = 1, otherwise tie to DGND.
13 DB4/DCIN B input Parallel data bit 4 in parallel mode; daisy-chain input B when SER/PAR SEL = 1 and DCEN = 1, otherwise tie to DGND.
14 DB3/DCIN C input Parallel data bit 3 in parallel mode; daisy-chain input C when SER/PAR SEL = 1 and DCEN = 1, otherwise tie to DGND.
15 DB2/SEL C bidirectional Parallel data bit 2 in parallel mode; SEL C serial interface configuration input in serial mode, enabling DOUT C when set to 1.
16 DB1/SEL B bidirectional Parallel data bit 1 in parallel mode; SEL B serial interface configuration input in serial mode, enabling DOUT B when set to 1.
17 DB0/SEL A bidirectional Parallel data bit 0 in parallel mode; SEL A serial interface configuration input in serial mode, always set to 1 in serial mode.
18 BUSY output Goes high when a conversion starts and stays high until conversion data is latched; CONVST edges are ignored while high.
19 CS input Active-low chip select that frames parallel reads and writes or the serial read transfer.
20 RD input Active-low read strobe that enables the parallel output bus when CS is also low; held low in serial mode.
21 CONVST C input Conversion start input that initiates simultaneous conversions on V5 and V6 on a low-to-high edge.
22 CONVST B input Conversion start input that initiates simultaneous conversions on V3 and V4 on a low-to-high edge.
23 CONVST A input Conversion start input that initiates simultaneous conversions on V1 and V2 on a low-to-high edge.
24 STBY input Standby mode input that places all six ADCs into standby when low and is high for normal operation.
25 DGND power_in Digital ground reference for all digital circuitry; connect to the DGND plane and keep within 0.3 V of AGND.
26 DVCC power_in Digital power supply specified at 4.75 V to 5.25 V; decouple to DGND with a 1 µF capacitor and keep within 0.3 V of AVCC.
27 RANGE input Hardware input range select sampled at the falling edge of BUSY: logic 1 selects ±2 × VREF and logic 0 selects ±4 × VREF.
28 RESET input Active-high reset that requires a pulse after power-up, typically 100 ns wide.
29 W/B input Word/byte select: logic low selects 16-bit word transfers on DB[15:0] and logic high selects byte mode; tie to DGND in serial mode.
30 VSS power_in Negative analog input supply, −10 V to −16.5 V for the ±4 × VREF range or −5 V to −16.5 V for the ±2 × VREF range.
31 VDD power_in Positive analog input supply, 10 V to 16.5 V for the ±4 × VREF range or 5 V to 16.5 V for the ±2 × VREF range.
32 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
33 V1 passive Single-ended analog input channel 1 with range set by RANGE pin in hardware mode or RNGA bits in software mode.
34 AVCC power_in Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
35 AVCC power_in Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
36 V2 passive Single-ended analog input channel 2 with range set by RANGE pin in hardware mode or RNGB bits in software mode.
37 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
38 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
39 V3 passive Single-ended analog input channel 3 with range set by RANGE pin in hardware mode or RNGA bits in software mode.
40 AVCC power_in Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
41 AVCC power_in Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
42 V4 passive Single-ended analog input channel 4 with range set by RANGE pin in hardware mode or RNGB bits in software mode.
43 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
44 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
45 V5 passive Single-ended analog input channel 5 with range set by RANGE pin in hardware mode or RNGC bits in software mode.
46 AVCC power_in Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
47 AVCC power_in Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
48 V6 passive Single-ended analog input channel 6 with range set by RANGE pin in hardware mode or RNGC bits in software mode.
49 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
50 AVCC power_in Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
51 REFIN/REFOUT passive On-chip 2.5 V reference output, or external reference input when the internal reference is disabled; decouple with at least 1 µF when enabled.
52 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
53 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
54 REFCAPA passive Reference buffer decoupling pin for ADC pair A; decouple to AGND with a 1 µF capacitor.
55 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
56 REFCAPB passive Reference buffer decoupling pin for ADC pair B; decouple to AGND with a 1 µF capacitor.
57 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
58 REFCAPC passive Reference buffer decoupling pin for ADC pair C; decouple to AGND with a 1 µF capacitor.
59 AGND power_in Analog ground reference for all analog circuitry; refer all analog inputs and external references to this pin.
60 AVCC power_in Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
61 SER/PAR SEL input Selects the parallel interface when low and the serial interface when high.
62 H/S SEL input Hardware/software select: logic 0 selects hardware mode with CONVST-selected pairs and logic 1 selects software mode via the control register.
63 WR/REFEN/DIS input Write strobe for the control register when H/S SEL is high; enables or disables the internal reference when H/S SEL is low.
64 DB15 bidirectional Parallel data bit 15 used to output the conversion result or write the control register; tie to DGND in serial mode.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-64(10x10)
Category Data Converters
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Signal-to-(Noise + Distortion) (SINAD) SINAD 73.5 dB fIN = 10 kHz sine wave 7
Differential Nonlinearity DNL -0.7 0.7 LSB 7
Integral Nonlinearity INL -0.5 0.5 LSB 7
Positive Full-Scale Error -0.95 0.95 % FSR 7
Positive Full-Scale Error Matching -0.366 0.366 % FSR 7
Bipolar Zero-Scale Error -2 2 LSB 7
Bipolar Zero-Scale Error Matching -2 2 LSB 7
Negative Full-Scale Error -0.95 0.95 % FSR 7
Negative Full-Scale Error Matching -0.366 0.366 % FSR 7
DC Leakage Current -1 1 µA 7
Reference Input Voltage Range 2.5 2.5 V 7
Reference Output Voltage 2.49 2.51 V 7
Input Current IIN -10 10 µA Typically 10 nA, VIN = 0 V or VDRIVE 7
Floating-State Leakage Current -10 10 µA 8
Output Low Voltage VOL 0.2 V ISINK = 200 µA 8
AVCC Analog Supply Voltage AVCC 4.75 5.25 V 8
DVCC Digital Supply Voltage DVCC 4.75 5.25 V 8
VDRIVE Logic Power Supply VDRIVE 2.7 5.25 V 8
Positive Analog Supply Voltage VDD -5 16.5 V For the 4 × VREF range, VDD = 10 V to 16.5 V 8
Negative Analog Supply Voltage VSS -16.5 -5 V For the 4 × VREF range, VSS = −10 V to −16.5 V 8
Track-and-Hold Acquisition Time tACQ 550 ns Acquisition time, VDRIVE = 2.7 V to 5.25 V 9
Minimum quiet time between bus relinquish and start of next conversion tQUIET 150 ns 9
Minimum CONVST low pulse t10 25 ns 9
CONVST high to BUSY high t1 60 ns 9
STBY rising edge to CONVST rising edge tWAKE-UP 2 ms 9
Wake-up from partial power-down mode tWAKE-UP 25 µs Partial power-down mode 9
BUSY to RD delay t2 0 ns 9
CS to RD setup time t3 0 ns 9
CS to RD hold time t4 0 ns 9
RD pulse width t5 45 ns VDRIVE < 4.75 V 9
RD pulse width t5 36 ns VDRIVE = 4.75 V to 5.25 V 9
Data access time after RD falling edge t6 45 ns VDRIVE < 4.75 V 9
Data access time after RD falling edge t6 36 ns VDRIVE = 4.75 V to 5.25 V 9
Data hold time after RD rising edge t7 10 ns 9
Bus relinquish time after RD rising edge t8 12 ns 9
Minimum time between reads t9 6 ns 9
WR pulse width t11 15 ns 9
CS to WR setup time t12 0 ns 9
Data setup time before WR rising edge t14 5 ns 9
Frequency of serial read clock fSCLK 18 MHz 9
Delay from CS until DOUTx three-state disabled t16 12 ns 9
Data access time after SCLK rising edge/CS falling edge t17 22 ns 9
SCLK to data valid hold time after SCLK falling edge t20 10 ns 9
CS rising edge to DOUTx high impedance t21 18 ns 9
VDD to AGND, DGND VDD -0.3 16.5 V 10
VSS to AGND, DGND VSS -16.5 0.3 V 10
AVCC to AGND, DGND AVCC -0.3 7 V 10
DVCC to DGND, AGND DVCC -0.3 7 V 10
AGND to DGND -0.3 0.3 V 10
Input Current to Any Pin Except Supplies -10 10 mA Transient currents of up to 100 mA do not cause SCR latch-up 10
Operating Temperature Range (Y Version) TA -40 125 °C 10
Storage Temperature Range -65 150 °C 10
Junction Temperature 150 °C 10
Thermal Resistance, junction-to-ambient, 64-Lead LQFP θJA 45 °C/W Device soldered in 4-layer circuit board 10
Thermal Resistance, junction-to-case, 64-Lead LQFP θJC 11 °C/W 10

CAD (KiCad official)

  • Symbol: AD7658YSTZ-1
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ad7658ystz-1-etched.step / ad7658ystz-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7658ystz-1.step / ad7658ystz-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 6ed754dce830790a, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF