SN75ALS193N from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1B	input	Inverting differential receiver input for channel 1, with ±200 mV input sensitivity over a common-mode range of -7 V to 7 V and 12 kΩ minimum input resistance.
2	1A	input	Non-inverting differential receiver input for channel 1, with ±200 mV input sensitivity over a common-mode range of -7 V to 7 V and 12 kΩ minimum input resistance.
3	1Y	tri_state	3-state receiver output for channel 1 that goes high-impedance when the enables are inactive and is high for open inputs; recommended IOL up to 16 mA and IOH down to -400 µA.
4	G	input	Active-high enable input common to all four receiver channels; recommended VIH minimum 2 V and VIL maximum 0.8 V.
5	2Y	tri_state	3-state receiver output for channel 2 that goes high-impedance when the enables are inactive and is high for open inputs; recommended IOL up to 16 mA and IOH down to -400 µA.
6	2A	input	Non-inverting differential receiver input for channel 2, with ±200 mV input sensitivity over a common-mode range of -7 V to 7 V and 12 kΩ minimum input resistance.
7	2B	input	Inverting differential receiver input for channel 2, with ±200 mV input sensitivity over a common-mode range of -7 V to 7 V and 12 kΩ minimum input resistance.
8	GND	power_in	Ground reference for the device; all voltages except differential input voltage are referenced to network ground.
9	3B	input	Inverting differential receiver input for channel 3, with ±200 mV input sensitivity over a common-mode range of -7 V to 7 V and 12 kΩ minimum input resistance.
10	3A	input	Non-inverting differential receiver input for channel 3, with ±200 mV input sensitivity over a common-mode range of -7 V to 7 V and 12 kΩ minimum input resistance.
11	3Y	tri_state	3-state receiver output for channel 3 that goes high-impedance when the enables are inactive and is high for open inputs; recommended IOL up to 16 mA and IOH down to -400 µA.
12	G	input	Active-low enable input (overbar lost in text extraction) common to all four receiver channels; recommended VIH minimum 2 V and VIL maximum 0.8 V.
13	4Y	tri_state	3-state receiver output for channel 4 that goes high-impedance when the enables are inactive and is high for open inputs; recommended IOL up to 16 mA and IOH down to -400 µA.
14	4A	input	Non-inverting differential receiver input for channel 4, with ±200 mV input sensitivity over a common-mode range of -7 V to 7 V and 12 kΩ minimum input resistance.
15	4B	input	Inverting differential receiver input for channel 4, with ±200 mV input sensitivity over a common-mode range of -7 V to 7 V and 12 kΩ minimum input resistance.
16	VCC	power_in	Single 5 V supply; recommended supply voltage is 4.75 V minimum, 5 V nominal, and 5.25 V maximum.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	PDIP-16
Category	Interface ICs
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	4.75	5	5.25	V		3
Common-mode input voltage	VIC	-7		7	V		3
Differential input voltage	VID	-12		12	V		3
High-level input voltage	VIH	2			V		3
Low-level input voltage	VIL			0.8	V		3
High-level output current	IOH			-400	µA		3
Low-level output current	IOL			16	mA		3
Operating free-air temperature	TA	0		70	°C		3
Supply voltage (absolute maximum)	VCC			7	V	see Note 1	3
Input voltage (A or B)	VI	-15		15	V		3
Differential input voltage (absolute maximum)	VID	-15		15	V	see Note 2	3
Enable input voltage	VI			7	V		3
Low-level output current (absolute maximum)	IOL			50	mA		3
Operating free-air temperature range (absolute maximum)	TA	0		70	°C		3
Storage temperature range	Tstg	-65		150	°C		3
Lead temperature				300	°C	1,6 mm (1/16 inch) from case for 60 seconds	3
Power rating, N package				1150	mW	TA ≤ 25°C	3
Power rating, N package at TA = 70°C				736	mW	TA = 70°C	3
Threshold voltage, positive-going input	VIT+			200	mV		4
Threshold voltage, negative-going input	VIT-	-200			mV		4
Enable-input clamp voltage	VIK			-1.5	V	VCC = MIN, II = -18 mA	4
High-level output voltage	VOH	2.5	3.6		V	VCC = MIN, VID = 200 mV, IOH = -400 µA, See Figure 1	4
Low-level output voltage (IOL = 8 mA)	VOL			0.45	V	VCC = MIN, VID 200 mV, IOL = 8 mA	4
Low-level output voltage (IOL = 16 mA)	VOL			0.5	V	VID = -200 mV, IOL = 16 mA, See Figure 1	4
High-impedance state output current (VO = 2.4 V)	IOZ			20	µA	VCC = MAX, VO = 2.4 V	4
High-impedance state output current (VO = 0.4 V)	IOZ	-20			µA	VCC = MAX, VO = 0.4 V	4
Line input current (VI = 15 V)	II		0.7	1.2	mA	Other input at 0, VCC = MIN, VI = 15 V, See Note 3	4
Line input current (VI = -15 V)	II		-1	-1.7	mA	Other input at 0, VCC = MIN, VI = -15 V, See Note 3	4
High-level enable input current (VIH = 2.7 V)	IIH			20	µA	VCC = MAX, VIH = 2.7 V	4
High-level enable input current (VIH = MAX)	IIH			100	µA	VCC = MAX, VIH = MAX	4
Low-level enable input current	IIL			-100	µA	VCC = MAX, VIL = 0.4 V	4
Input resistance	rI	12	18		kΩ		4
Short-circuit output current	IOS	-15	-78	-130	mA	VCC = MAX, VO = 0, VID = 3 V, See Note 4	4
Supply current	ICC		22	35	mA	VCC = MAX, Outputs disabled	4
Propagation delay time, low-to-high-level output	tPLH		15	22	ns	VID = -2.5 V to 2.5 V, CL = 15 pF, See Figure 2	4
Propagation delay time, high-to-low-level output	tPHL		15	22	ns	CL = 15 pF, See Figure 2	4
Output enable time to high level	tPZH		13	25	ns	CL = 15 pF, See Figure 3	4
Output enable time to low level	tPZL		11	25	ns	CL = 15 pF, See Figure 3	4
Output disable time from high level	tPHZ		13	25	ns	CL = 5 pF, See Figure 3	4
Output disable time from low level	tPLZ		15	22	ns	CL = 5 pF, See Figure 3	4
Hysteresis voltage (VIT+, VIT-)	Vhys		120		mV		4
Derating factor above TA = 25°C, N package			9.2		mW/°C	above TA = 25°C	3

CAD (KiCad official)

Symbol: SN75ALS193N
Footprint: Package_DIP:DIP-16_W7.62mm
3D model: PDIP-16 (KiCad packages3D, STEP)
3D model files: sn75als193n-etched.step / sn75als193n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn75als193n.step / sn75als193n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (19 pp, sha256 1cfec37ed19df51b, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

SN75ALS193N

Verified SN75ALS193N

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3D Model

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