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PCM1808QPWRQ1

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Texas Instruments ADCs/DACs - Special Purpose, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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PCM1808QPWRQ1

Texas Instruments · ADCs/DACs - Special Purpose · TSSOP-14

PCM1808QPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in Reference voltage decoupling pin, nominally 0.5 VCC, which requires decoupling and is not a supply output.
2 AGND power_in Analog ground; the difference between AGND and DGND is limited to ±0.1 V.
3 VCC power_in Analog power supply, 5 V; recommended range 4.5 V to 5.5 V with an absolute maximum of 6.5 V.
4 VDD power_in Digital power supply, 3.3 V; recommended range 2.7 V to 3.6 V with an absolute maximum of 4 V.
5 DGND power_in Digital ground; the difference between DGND and AGND is limited to ±0.1 V.
6 SCKI input System clock input at 256 fS, 384 fS or 512 fS, Schmitt-trigger input that is 5-V tolerant, with system clock limited to 2.048 MHz to 49.152 MHz.
7 LRCK bidirectional Audio data latch enable (word clock) input/output, Schmitt-trigger input with internal 50 kΩ typical pulldown; sampling rate 8 kHz to 96 kHz.
8 BCK bidirectional Audio data bit clock input/output, Schmitt-trigger input with internal 50 kΩ typical pulldown.
9 DOUT output Audio data digital output; recommended digital output load capacitance is 20 pF.
10 MD0 input Audio interface mode select 0, Schmitt-trigger input with internal 50 kΩ typical pulldown and 5-V tolerant.
11 MD1 input Audio interface mode select 1, Schmitt-trigger input with internal 50 kΩ typical pulldown and 5-V tolerant.
12 FMT input Audio interface format select, Schmitt-trigger input with internal 50 kΩ typical pulldown and 5-V tolerant.
13 VINL input Analog input for the L channel, single-ended with 0.6 VCC typical input voltage (2.93 Vp-p to 3.23 Vp-p full scale at VCC = 5 V) and 60 kΩ typical input impedance.
14 VINR input Analog input for the R channel, single-ended with 0.6 VCC typical input voltage (2.93 Vp-p to 3.23 Vp-p full scale at VCC = 5 V) and 60 kΩ typical input impedance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Data Acquisition
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage, VCC VCC -0.3 6.5 V over operating free-air temperature range 2
Digital supply voltage, VDD VDD -0.3 4 V over operating free-air temperature range 2
Ground voltage differences, AGND, DGND -0.1 0.1 V 2
Digital input voltage, LRCK, BCK, DOUT -0.3 4 V (VDD + 0.3 V) < 4 V as printed 2
Digital input voltage, SCKI, MD0, MD1, FMT -0.3 6.5 V 2
Analog input voltage, VINL, VINR, VREF -0.3 6.5 V (VCC + 0.3 V) < 6.5 V as printed 2
Input current (any pins except supplies) -10 10 mA 2
Ambient temperature under bias, TA TA -40 125 °C 2
Storage temperature, Tstg Tstg -55 150 °C 2
Junction temperature, TJ TJ 150 °C 2
Lead temperature (soldering) 260 °C 5 s 2
Package temperature (reflow, peak) 260 °C 2
Analog supply voltage, VCC VCC 4.5 5 5.5 V 2
Digital supply voltage, VDD VDD 2.7 3.3 3.6 V 2
Analog input voltage, full scale (-0 dB) 2.93 3 3.23 Vp-p VCC = 5 V 2
Digital input clock frequency, system clock 2.048 49.152 MHz 2
Digital input clock frequency, sampling clock 8 96 kHz 2
Digital output load capacitance 20 pF 2
Operating free-air temperature, TA TA -40 125 °C 2
Sampling frequency, fS fS 8 48 96 kHz 3
System clock frequency, 256 fS 2.048 12.288 24.576 MHz -40°C ≤ TA ≤ 125°C 3
System clock frequency, 384 fS 3.072 18.432 36.864 MHz -40°C ≤ TA ≤ 125°C 3
System clock frequency, 512 fS 4.096 24.576 49.152 MHz -40°C ≤ TA ≤ 125°C 3
High-level input logic voltage, VIH VIH 2 VDC 3
Low-level input logic voltage, VIL VIL 0 0.8 VDC 3
High-level input logic voltage, VIH VIH 2 5.5 VDC -40°C ≤ TA ≤ 125°C 3
Input logic current, IIH IIH -10 10 µA VIN = VDD 3
Input logic current, IIL IIL -10 10 µA VIN = 0 V 3
Input logic current, IIH IIH 65 100 µA VIN = VDD, at 25°C 3
Input logic current, IIH IIH 65 150 µA VIN = VDD, -40°C ≤ TA ≤ 125°C 3
High-level output logic voltage, VOH VOH 2.8 VDC IOUT = -4 mA, at 25°C 3
High-level output logic voltage, VOH VOH 2.7 VDC IOUT = -4 mA, -40°C ≤ TA ≤ 125°C 3
Low-level output logic voltage, VOL VOL 0.5 VDC IOUT = 4 mA, -40°C ≤ TA ≤ 125°C 3
Gain mismatch, channel-to-channel -3 1 3 % of FSR -40°C ≤ TA ≤ 125°C 3
Gain error -6 3 6 % of FSR -40°C ≤ TA ≤ 125°C 3
THD+N THD+N -93 -87 dB VIN = -0.5 dB, fS = 48 kHz, at 25°C 3
THD+N THD+N -93 -85 dB VIN = -0.5 dB, fS = 48 kHz, -40°C ≤ TA ≤ 125°C 3
Dynamic range, A-weighted 95 99 dB fS = 48 kHz, at 25°C 3
Dynamic range, A-weighted 93 99 dB fS = 48 kHz, -40°C ≤ TA ≤ 125°C 3
Signal-to-noise ratio, A-weighted S/N 95 99 dB fS = 48 kHz, at 25°C 3
Signal-to-noise ratio, A-weighted S/N 93 99 dB fS = 48 kHz, -40°C ≤ TA ≤ 125°C 3
Channel separation 93 97 dB fS = 48 kHz, at 25°C 4
Channel separation 91 97 dB fS = 48 kHz, -40°C ≤ TA ≤ 125°C 4
Pass-band ripple -0.05 0.05 dB 4
Input voltage 0.58 0.6 0.65 VCC -40°C ≤ TA ≤ 125°C 4
Center voltage input range 0.2 0.5 0.8 V -40°C ≤ TA ≤ 125°C 4
VCC voltage range VCC 4.5 5 5.5 V 4
VDD voltage range VDD 2.7 3.3 3.6 VDC -40°C ≤ TA ≤ 125°C 4
Supply current ICC 8.6 11 mA fS = 48 kHz, 96 kHz, -40°C ≤ TA ≤ 125°C 4
Supply current IDD 5.9 8 mA fS = 48 kHz, at 25°C 4
Supply current IDD 5.9 10 mA fS = 48 kHz, -40°C ≤ TA ≤ 125°C 4
Power dissipation 62 81 mW fS = 48 kHz 4
Operation temperature, TA TA -40 125 °C 4
Thermal resistance, θJA θJA 170 °C/W 4
System clock pulse duration, HIGH, tw(SCKH) tw(SCKH) 8 ns 11
System clock pulse duration, LOW, tw(SCKL) tw(SCKL) 8 ns 11
System clock duty cycle 40 60 % 11

CAD (KiCad official)

  • Symbol: PCM1808QPWRQ1
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: pcm1808qpwrq1-etched.step / pcm1808qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pcm1808qpwrq1.step / pcm1808qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 1f5a5e2f7ce5059c, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF