component
MCP607-I
Public Made by Adomby adom
Microchip Tech Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownMCP607-I
Microchip Tech · Operational Amplifier · SOIC-8
MCP607-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Output of op amp A; it is a low-impedance voltage source, and in normal operation the output stays between VSS and VDD. |
| 2 | VINA- | input | Inverting input of op amp A; it is a high-impedance CMOS input with low bias current. |
| 3 | VINA+ | input | Non-inverting input of op amp A; for normal operation the input voltage must stay between VSS - 0.3V and VDD + 0.3V. |
| 4 | VSS | power_in | Negative power supply pin; VDD must be 2.5V to 5.5V higher than VSS, and in single-supply use VSS is connected to ground. |
| 5 | VINB+ | input | Non-inverting input of op amp B; it is a high-impedance CMOS input with low bias current, with input voltage limited to VSS - 0.3V to VDD + 0.3V. |
| 6 | VINB- | input | Inverting input of op amp B; it is a high-impedance CMOS input with low bias current. |
| 7 | VOUTB | output | Output of op amp B; it is a low-impedance voltage source, and in normal operation the output stays between VSS and VDD. |
| 8 | VDD | power_in | Positive power supply pin; it is 2.5V to 5.5V higher than VSS and needs bypass capacitors. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS | -250 | 250 | µV | 3 | ||
| Power Supply Rejection Ratio | PSRR | 80 | 93 | dB | 3 | ||
| Input Bias Current at Temperature | IB | 80 | pA | TA = +85°C | 3 | ||
| Common Mode Input Range, low limit (VSS, 0.3 V, VSS = GND) | VCMR | -0.3 | V | CMRR ≥ 75 dB | 3 | ||
| Common Mode Input Range, high limit (VDD, 1.1 V, relative to VDD) | VCMR | -1.1 | V | CMRR ≥ 75 dB | 3 | ||
| Common Mode Rejection Ratio | CMRR | 75 | 91 | dB | VDD = 5V, VCM = -0.3V to 3.9V | 3 | |
| DC Open-Loop Gain (Large-signal), RL = 25 kΩ | AOL | 105 | 121 | dB | RL = 25 kΩ to VL, VOUT = 50 mV to VDD, 50 mV | 3 | |
| DC Open-Loop Gain (Large-signal), RL = 5 kΩ | AOL | 100 | 118 | dB | RL = 5 kΩ to VL, VOUT = 0.1V to VDD, 0.1V | 3 | |
| Maximum Output Voltage Swing, low (VSS + 15 mV, RL = 25 kΩ) | VOL | 15 | mV | RL = 25 kΩ to VL, 0.5V input overdrive | 3 | ||
| Maximum Output Voltage Swing, high (VDD, 20 mV, RL = 25 kΩ, relative to VDD) | VOH | -20 | mV | RL = 25 kΩ to VL, 0.5V input overdrive | 3 | ||
| Maximum Output Voltage Swing, low (VSS + 45 mV, RL = 5 kΩ) | VOL | 45 | mV | RL = 5 kΩ to VL, 0.5V input overdrive | 3 | ||
| Maximum Output Voltage Swing, high (VDD, 60 mV, RL = 5 kΩ, relative to VDD) | VOH | -60 | mV | RL = 5 kΩ to VL, 0.5V input overdrive | 3 | ||
| Linear Output Voltage Range, low (VSS + 50 mV, RL = 25 kΩ) | VOUT | 50 | mV | RL = 25 kΩ to VL, AOL ≥ 105 dB | 3 | ||
| Linear Output Voltage Range, high (VDD, 50 mV, RL = 25 kΩ, relative to VDD) | VOUT | -50 | mV | RL = 25 kΩ to VL, AOL ≥ 105 dB | 3 | ||
| Linear Output Voltage Range, low (VSS + 100 mV, RL = 5 kΩ) | VOUT | 100 | mV | RL = 5 kΩ to VL, AOL ≥ 100 dB | 3 | ||
| Linear Output Voltage Range, high (VDD, 100 mV, RL = 5 kΩ, relative to VDD) | VOUT | -100 | mV | RL = 5 kΩ to VL, AOL ≥ 100 dB | 3 | ||
| Supply Voltage | VDD | 2.5 | 6 | V | 3 | ||
| Quiescent Current per Amplifier | IQ | 18.7 | 25 | µA | IO = 0 | 3 | |
| Specified Temperature Range | TA | -40 | 85 | °C | 5 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | Note 1 | 5 | |
| Storage Temperature Range | TA | -65 | 150 | °C | 5 | ||
| Supply Voltage (VDD, VSS) | 7 | V | 3 | ||||
| Current at Input Pins | -2 | 2 | mA | 3 | |||
| Analog Inputs (VIN+, VIN-), low limit (VSS, 1.0 V) | -1 | V | 3 | ||||
| Analog Inputs (VIN+, VIN-), high limit (VDD + 1.0 V) | 1 | V | 3 | ||||
| All Other Inputs and Outputs, low limit (VSS, 0.3 V) | -0.3 | V | 3 | ||||
| All Other Inputs and Outputs, high limit (VDD + 0.3 V) | 0.3 | V | 3 | ||||
| Current at Output and Supply Pins | -30 | 30 | mA | 3 | |||
| Storage Temperature (absolute maximum) | -65 | 150 | °C | 3 | |||
| Maximum Junction Temperature (TJ) | TJ | 150 | °C | 3 | |||
| ESD Protection On All Pins (HBM) | 3 | kV | 3 | ||||
| ESD Protection On All Pins (MM) | 200 | V | 3 | ||||
| Thermal Resistance, 8L-SOIC | θJA | 149.5 | °C/W | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | P = Plastic DIP (300 mil Body), 8-lead, 14-lead SN = Plastic SOIC (3.90 mm body), 8-lead | 39 |
CAD (KiCad official)
- Symbol:
MCP607-I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp607-i-etched.step/mcp607-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp607-i.step/mcp607-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (42 pp, sha256
d6c54507be187971, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).