component
AD5338RBCPZ-RL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5338RBCPZ-RL7
Analog Devices · Digital To Analog Converters (DACs) · LFCSP-16(3x3)
AD5338RBCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A with rail-to-rail output amplifier operation. |
| 2 | GND | power_in | Ground reference point for all circuitry on the part. |
| 3 | VDD | power_in | Power supply input operating from 2.7 V to 5.5 V, decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 4 | NC | unconnected | No connect; do not connect to this pin. |
| 5 | VOUTB | output | Analog output voltage from DAC B with rail-to-rail output amplifier operation. |
| 6 | SDA | bidirectional | Bidirectional open-drain serial data line used with SCL to clock data into or out of the 24-bit input shift register, needing an external pull-up resistor to the supply. |
| 7 | LDAC | input | Load DAC input operable in asynchronous or synchronous mode; pulsing low updates DAC registers so both outputs update simultaneously, and it can be tied permanently low. |
| 8 | GAIN | input | Gain select: tied to GND gives 0 V to VREF output span, tied to VLOGIC gives 0 V to 2 × VREF span for both DACs. |
| 9 | VLOGIC | power_in | Digital power supply with voltage range from 1.62 V to 5.5 V. |
| 10 | A0 | input | Address input that sets the first LSB of the 7-bit slave address. |
| 11 | SCL | input | Serial clock line used with SDA to clock data into or out of the 24-bit input register. |
| 12 | A1 | input | Address input that sets the second LSB of the 7-bit slave address. |
| 13 | RESET | input | Falling-edge-sensitive asynchronous reset input that ignores LDAC pulses while low and loads zero scale or midscale per RSTSEL; POR does not initialize correctly if forced low at power-up until released. |
| 14 | RSTSEL | input | Power-on reset select: tied to GND powers up both DACs to zero scale, tied to VLOGIC powers up to midscale. |
| 15 | VREF | power_in | Common reference pin that is the reference output when using the internal reference (default) and the reference input when using an external reference. |
| 16 | NC | unconnected | No connect; do not connect to this pin. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy | INL | -0.5 | 0.12 | 0.5 | LSB | 4 | |
| Differential Nonlinearity | DNL | -0.5 | 0.5 | LSB | Guaranteed monotonic by design | 4 | |
| Zero-Code Error | 0.4 | 1.5 | mV | All 0s loaded to DAC register | 4 | ||
| Offset Error | -1.5 | 0.1 | 1.5 | mV | 4 | ||
| Full-Scale Error | -0.1 | 0.01 | 0.1 | % of FSR | All 1s loaded to DAC register | 4 | |
| Gain Error | -0.1 | 0.02 | 0.1 | % of FSR | 4 | ||
| Total Unadjusted Error (external reference) | TUE | -0.1 | 0.01 | 0.1 | % of FSR | External reference; gain = 2; TSSOP | 4 |
| Total Unadjusted Error (internal reference) | TUE | -0.2 | 0.2 | % of FSR | Internal reference; gain = 1; TSSOP | 4 | |
| Reference Output Voltage | VREF | 2.4975 | 2.5 | 2.5025 | V | At ambient | 4 |
| Reference Temperature Coefficient | 2 | 5 | ppm/°C | Box method; characterized -40°C to +105°C | 4 | ||
| Input Low Voltage | VINL | 0.3 | V | 0.3 × VLOGIC | 4 | ||
| Input High Voltage | VINH | 0.7 | V | 0.7 × VLOGIC | 4 | ||
| Logic Input Current | -2 | 2 | µA | Per pin | 4 | ||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 3 mA | 5 | ||
| VLOGIC | VLOGIC | 1.8 | 5.5 | V | 5 | ||
| ILOGIC | ILOGIC | 3 | µA | 5 | |||
| VDD (gain = 1) | VDD | 2.7 | 5.5 | V | Gain = 1 | 5 | |
| IDD normal mode, internal reference off | IDD | 0.59 | 0.7 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; internal reference off | 5 | |
| IDD normal mode, internal reference on | IDD | 1.1 | 1.3 | mA | Internal reference on, at full scale | 5 | |
| IDD power-down, -40°C to +85°C | IDD | 1 | 4 | µA | -40°C to +85°C | 5 | |
| IDD power-down, -40°C to +105°C | IDD | 6 | µA | -40°C to +105°C | 5 | ||
| Output Voltage Settling Time | 5 | 7 | µs | ¼ to ¾ scale settling to ±2 LSB | 5 | ||
| SCL cycle time | t1 | 2.5 | µs | 6 | |||
| SCL high time | t2 | 0.6 | µs | tHIGH | 6 | ||
| SCL low time | t3 | 1.3 | µs | tLOW | 6 | ||
| Start/repeated start hold time | t4 | 0.6 | µs | tHD,STA | 6 | ||
| Data setup time | t5 | 100 | ns | tSU,DAT | 6 | ||
| Data hold time | t6 | 0 | 0.9 | µs | tHD,DAT | 6 | |
| Setup time for repeated start | t7 | 0.6 | µs | tSU,STA | 6 | ||
| Stop condition setup time | t8 | 0.6 | µs | tSU,STO | 6 | ||
| Bus free time | t9 | 1.3 | µs | between a stop and a start condition, tBUF | 6 | ||
| Rise time of SCL and SDA | t10 | 0 | 300 | ns | when receiving, tR | 6 | |
| Fall time of SDA and SCL | t11 | 300 | ns | min 20 + 0.1CB; transmitting/receiving, tF | 6 | ||
| LDAC pulse width | t12 | 20 | ns | 6 | |||
| SCL rising edge to LDAC rising edge | t13 | 400 | ns | 6 | |||
| Capacitive load for each bus line | CB | 400 | pF | 6 | |||
| VDD to GND | VDD | -0.3 | 7 | V | TA = 25°C | 7 | |
| VLOGIC to GND | VLOGIC | -0.3 | 7 | V | TA = 25°C | 7 | |
| VOUT to GND | VOUT | -0.3 | V | -0.3 V to VDD + 0.3 V | 7 | ||
| VREF to GND | VREF | -0.3 | V | -0.3 V to VDD + 0.3 V | 7 | ||
| Digital Input Voltage to GND | -0.3 | V | -0.3 V to VLOGIC + 0.3 V; excluding SDA and SCL | 7 | |||
| SDA and SCL to GND | -0.3 | 7 | V | 7 | |||
| Operating Temperature Range | -40 | 105 | °C | 7 | |||
| Storage Temperature Range | -65 | 150 | °C | 7 | |||
| Junction Temperature | 125 | °C | 7 | ||||
| Thermal Impedance, 16-Lead LFCSP | θJA | 70 | °C/W | 0 Airflow, 4-Layer Board | 7 | ||
| Reflow Soldering Peak Temperature, Pb Free | 260 | °C | J-STD-020 | 7 | |||
| Offset Error Drift | 1 | µV/°C | ±1 typ; guaranteed by design | 4 | |||
| Gain Temperature Coefficient | 1 | ppm Of FSR/°C | ±1 typ; guaranteed by design | 4 |
CAD (KiCad official)
- Symbol:
AD5338RBCPZ-RL7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
ad5338rbcpz-rl7-etched.step/ad5338rbcpz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5338rbcpz-rl7.step/ad5338rbcpz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (27 pp, sha256
c4a0b462cf5e181d, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).