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TPS54429PWPR

Texas Instruments · DC-DC Converters · HTSSOP-14-EP

TPS54429PWPR from Texas Instruments, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VO input Connect to output of converter. Sense input used for on-time adjustment and for output discharge through the internal 50 Ω discharge MOSFET when disabled.
2 VFB input Converter feedback input. Connect to output voltage via a resistor divider; regulated to the internal 0.765 V reference (0.76 V to 5.5 V programmable output).
3 VREG5 power_out 5.5 V internal LDO output (up to ~70 mA). A ~1 µF ceramic capacitor to GND is required for stability. VREG5 is disabled when EN is low; it also feeds the internal UVLO (~3.8 V wake-up).
4 SS input Soft-start control. An external capacitor from SS to GND sets the soft-start ramp; charged by a 2 µA current source (Tss ≈ Css × 0.765 / 2 µA).
5 GND power_in Signal (analog) ground pin. Return for internal control circuitry; tie strongly to PGND near the IC.
6 PG output Open-drain power-good output. Goes high when VFB is within -10% of target (after 1.7 × soft-start); pulls low after ~5 µs delay if VFB drops below 85%. Recommended pull-up to VREG5 with 20 kΩ-150 kΩ; sink capability 2.5-5 mA.
7 EN input Enable control input, active high. Must be pulled up to enable the device (VIH ≥ 2 V, VIL ≤ 0.48 V). Rated up to 18 V; drives the device into shutdown (< ~2 µA) when low.
8 PGND1 power_in Power ground return for the low-side MOSFET. Also serves as an input of the current-limit comparator. Connect PGND1/PGND2 and GND together with a solid plane near the IC.
9 PGND2 power_in Power ground return for the low-side MOSFET (paralleled with PGND1). Also serves as an input of the current-limit comparator.
10 SW1 output Switch node between the integrated high-side and low-side N-channel MOSFETs (Rds(on) 63 mΩ high-side / 55 mΩ low-side). Connect the power inductor here. Also used as the current-sense input during the low-side on-time. Rated -1.8 V to 18 V (transient -3 V to 21 V).
11 SW2 output Switch node output paralleled with SW1 (internally tied to the same power stage). Connect together at the inductor. Also serves as an input to the current-limit comparator.
12 VBST power_in Bootstrap supply input for the high-side NFET gate driver. Connect a capacitor from VBST to SW1/SW2. An internal PN diode is connected from VREG5 to VBST. Rated up to 24 V (28 V transient).
13 VIN1 power_in Power input, connected to the drain of the high-side NFET. Also supplies the internal 5.5 V VREG5 linear regulator. Operating range 7 V to 18 V (abs max 20 V).
14 VIN2 power_in Power input paralleled with VIN1 (high-side NFET drain). Bypass VIN1/VIN2 together with a low-ESR input capacitor.
15 PowerPAD power_in Exposed thermal pad on the back side of the HTSSOP package. Must be soldered to the PCB for proper thermal dissipation and should be connected to PGND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-14-EP
Category Power Management (PMIC)
Pins 15

Ordering variants

Same part, different packaging or reel option.

  • TPS54429PWPR

CAD (KiCad official)

  • Symbol: TPS54429PWPR
  • Footprint: Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 3960456fc225b97f, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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