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SN74ALVC32DR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74ALVC32DR
Texas Instruments · Logic Gates · SOIC-14
SN74ALVC32DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A of quadruple 2-input positive-OR gate; VI = 0 to 3.6 V; unused inputs must be held at VCC or GND. |
| 2 | 1B | input | Gate 1 input B of quadruple 2-input positive-OR gate; VI = 0 to 3.6 V; unused inputs must be held at VCC or GND. |
| 3 | 1Y | output | Gate 1 output Y = 1A + 1B (positive logic); IOH = −24 mA / IOL = 24 mA at VCC = 3 V; tpd max 2.8 ns at 3.3 V. |
| 4 | 2A | input | Gate 2 input A of quadruple 2-input positive-OR gate; VI = 0 to 3.6 V; unused inputs must be held at VCC or GND. |
| 5 | 2B | input | Gate 2 input B of quadruple 2-input positive-OR gate; VI = 0 to 3.6 V; unused inputs must be held at VCC or GND. |
| 6 | 2Y | output | Gate 2 output Y = 2A + 2B (positive logic); IOH = −24 mA / IOL = 24 mA at VCC = 3 V; tpd max 2.8 ns at 3.3 V. |
| 7 | GND | power_in | Ground supply reference; continuous current through GND pin ±100 mA maximum. |
| 8 | 3Y | output | Gate 3 output Y = 3A + 3B (positive logic); IOH = −24 mA / IOL = 24 mA at VCC = 3 V; tpd max 2.8 ns at 3.3 V. |
| 9 | 3A | input | Gate 3 input A of quadruple 2-input positive-OR gate; VI = 0 to 3.6 V; unused inputs must be held at VCC or GND. |
| 10 | 3B | input | Gate 3 input B of quadruple 2-input positive-OR gate; VI = 0 to 3.6 V; unused inputs must be held at VCC or GND. |
| 11 | 4Y | output | Gate 4 output Y = 4A + 4B (positive logic); IOH = −24 mA / IOL = 24 mA at VCC = 3 V; tpd max 2.8 ns at 3.3 V. |
| 12 | 4A | input | Gate 4 input A of quadruple 2-input positive-OR gate; VI = 0 to 3.6 V; unused inputs must be held at VCC or GND. |
| 13 | 4B | input | Gate 4 input B of quadruple 2-input positive-OR gate; VI = 0 to 3.6 V; unused inputs must be held at VCC or GND. |
| 14 | VCC | power_in | Positive supply voltage; VCC = 1.65 V to 3.6 V recommended; ICC max 10 µA at 3.6 V with IO = 0; continuous current ±100 mA maximum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74ALVC32DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74alvc32dr-etched.step/sn74alvc32dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74alvc32dr.step/sn74alvc32dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (18 pp, sha256
6d33f3031369719e, retrieved 2026-09-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).