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SN74LVC00AQPWRG4Q1
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LVC00AQPWRG4Q1
Texas Instruments · Logic Gates · TSSOP-14
SN74LVC00AQPWRG4Q1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1, input A of the NAND gate; the datasheet gives input voltage range 0 to 5.5 V, so it can be driven from 3.3 V or 5 V logic. |
| 2 | 1B | input | Channel 1, input B of the NAND gate; the datasheet gives input voltage range 0 to 5.5 V, so it can be driven from 3.3 V or 5 V logic. |
| 3 | 1Y | output | Channel 1, NAND output Y; output voltage range is 0 V to VCC per the recommended operating conditions. |
| 4 | 2A | input | Channel 2, input A of the NAND gate; the datasheet gives input voltage range 0 to 5.5 V, so it can be driven from 3.3 V or 5 V logic. |
| 5 | 2B | input | Channel 2, input B of the NAND gate; the datasheet gives input voltage range 0 to 5.5 V, so it can be driven from 3.3 V or 5 V logic. |
| 6 | 2Y | output | Channel 2, NAND output Y; output voltage range is 0 V to VCC per the recommended operating conditions. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | output | Channel 3, NAND output Y; output voltage range is 0 V to VCC per the recommended operating conditions. |
| 9 | 3A | input | Channel 3, input A of the NAND gate; the datasheet gives input voltage range 0 to 5.5 V, so it can be driven from 3.3 V or 5 V logic. |
| 10 | 3B | input | Channel 3, input B of the NAND gate; the datasheet gives input voltage range 0 to 5.5 V, so it can be driven from 3.3 V or 5 V logic. |
| 11 | 4Y | output | Channel 4, NAND output Y; output voltage range is 0 V to VCC per the recommended operating conditions. |
| 12 | 4A | input | Channel 4, input A of the NAND gate; the datasheet gives input voltage range 0 to 5.5 V, so it can be driven from 3.3 V or 5 V logic. |
| 13 | 4B | input | Channel 4, input B of the NAND gate; the datasheet gives input voltage range 0 to 5.5 V, so it can be driven from 3.3 V or 5 V logic. |
| 14 | VCC | power_in | Positive supply; operating range is 2 V to 3.6 V, with 1.5 V for data retention only. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74LVC00AQPWRG4Q1 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74lvc00aqpwrg4q1-etched.step/sn74lvc00aqpwrg4q1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lvc00aqpwrg4q1.step/sn74lvc00aqpwrg4q1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
7cf6207e89662870, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).