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ADS8686SIPZAR

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Texas Instruments Analog To Digital Converters (ADC), LQFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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ADS8686SIPZAR

Texas Instruments · Analog To Digital Converters (ADC) · LQFP-80(14x14)

ADS8686SIPZAR from Texas Instruments, in a LQFP-80(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN_4BGND input Analog input channel 4B negative input; 0.3V differential range to AIN_4B
2 AIN_4B input Analog input channel 4B positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
3 AIN_5BGND input Analog input channel 5B negative input; 0.3V differential range to AIN_5B
4 AIN_5B input Analog input channel 5B positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
5 AGND power_in Analog ground pin; connect all AGND pins to analog ground plane
6 AVDD power_in Analog power pin 4.75V to 5.25V; connect to nearest AGND with 10µF and 0.1µF decoupling capacitors
7 AIN_6B input Analog input channel 6B positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
8 AIN_6BGND input Analog input channel 6B negative input; 0.3V differential range to AIN_6B
9 AIN_7B input Analog input channel 7B positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
10 AIN_7BGND input Analog input channel 7B negative input; 0.3V differential range to AIN_7B
11 AIN_7AGND input Analog input channel 7A negative input; 0.3V differential range to AIN_7A
12 AIN_7A input Analog input channel 7A positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
13 AIN_6AGND input Analog input channel 6A negative input; 0.3V differential range to AIN_6A
14 AIN_6A input Analog input channel 6A positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
15 AVDD power_in Analog power pin 4.75V to 5.25V; connect to nearest AGND with 10µF and 0.1µF decoupling capacitors
16 AGND power_in Analog ground pin; connect all AGND pins to analog ground plane
17 AIN_5A input Analog input channel 5A positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
18 AIN_5AGND input Analog input channel 5A negative input; 0.3V differential range to AIN_5A
19 AIN_4A input Analog input channel 4A positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
20 AIN_4AGND input Analog input channel 4A negative input; 0.3V differential range to AIN_4A
21 AIN_3AGND input Analog input channel 3A negative input; 0.3V differential range to AIN_3A
22 AIN_3A input Analog input channel 3A positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
23 AIN_2AGND input Analog input channel 2A negative input; 0.3V differential range to AIN_2A
24 AIN_2A input Analog input channel 2A positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
25 AIN_1AGND input Analog input channel 1A negative input; 0.3V differential range to AIN_1A
26 AIN_1A input Analog input channel 1A positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
27 AIN_0AGND input Analog input channel 0A negative input; 0.3V differential range to AIN_0A
28 AIN_0A input Analog input channel 0A positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
29 AGND power_in Analog ground pin; connect all AGND pins to analog ground plane
30 AVDD power_in Analog power pin 4.75V to 5.25V; connect to nearest AGND with 10µF and 0.1µF decoupling capacitors
31 REFCAP power_out Reference amplifier output pin; decoupled with 10µF low ESR ceramic capacitor to REFGND near the pin
32 REFGND power_in Reference ground pin; connect to AGND plane with shortest trace
33 REFIO bidirectional Internal 2.5V reference output when REFSEL high; external reference input when REFSEL low; decoupled with 0.1µF to REFIO_GND
34 REFIO_GND power_in REFIO ground pin; connect to AGND plane with shortest trace
35 REFSEL input Active high logic input to enable internal reference; state latched at RESET release
36 RESET input Active low logic input for device digital logic reset; pulse duration determines partial or full reset
37 SEQEN input Active high logic input to enable channel sequencer in hardware mode; state latched at RESET release
38 HW_RNGSEL1 input Hardware and software mode selection input; state latched at full reset for analog input range selection
39 HW_RNGSEL0 input Hardware and software mode selection input; state latched at full reset for analog input range selection
40 SER/BYTE/PAR input Logic input for interface mode selection between serial, parallel byte, or parallel modes; state latched at full reset
41 DB0 tri_state Data bus bit 0 (LSB) in parallel/byte modes; must connect to DGND in serial mode
42 DB1 tri_state Data bus bit 1 in parallel/byte modes; must connect to DGND in serial mode
43 DB2 tri_state Data bus bit 2 in parallel/byte modes; must connect to DGND in serial mode
44 DB3 tri_state Data bus bit 3 in parallel/byte modes; must connect to DGND in serial mode
45 DB4/SER1W tri_state Multifunctional pin: DB4 data in parallel/byte modes or serial 1-wire/2-wire mode selection; state latched at full reset
46 DB5/CRCEN tri_state Multifunctional pin: DB5 data in parallel/byte modes or CRC enable in serial mode; state latched at full reset
47 DB6 tri_state Data bus bit 6 in parallel/byte modes; must connect to DGND in serial mode
48 DB7 tri_state Data bus bit 7 in parallel/byte modes; must connect to DGND in serial mode
49 DVDD power_in Digital power pin 1.71V to AVDD; decoupled with minimum 0.1µF capacitor to DGND at pin 50
50 DGND power_in Digital ground pin; connect to digital ground plane
51 REGGNDD power_in Internal digital regulator ground pin; connect to DGND plane with shortest trace
52 REGCAPD power_out Internal digital regulator voltage output; decoupled with 10µF ceramic capacitor to REGGNDD near the pin
53 DB8 tri_state Multifunctional pin: DB8 data in parallel mode; must connect to DGND in byte/serial modes
54 DB9/BYTESEL tri_state Multifunctional pin: DB9 data in parallel modes or parallel byte interface enable; state latched at full reset
55 DB10/SDI tri_state Multifunctional pin: DB10 data in parallel modes or serial data input in software serial mode
56 DB11/SDOB tri_state Multifunctional pin: DB11 data in parallel modes or serial data output B when enabled; must connect to DGND in byte mode
57 DB12/SDOA tri_state Multifunctional pin: DB12 data in parallel modes or serial data output A in serial mode
58 DB13/OS0 tri_state Multifunctional pin: DB13 data in parallel modes or oversampling rate bit 0 in hardware serial mode
59 DB14/OS1 tri_state Multifunctional pin: DB14 data in parallel modes or oversampling rate bit 1 in hardware serial mode
60 DB15/OS2 tri_state Multifunctional pin: DB15 data (MSB) in parallel modes or oversampling rate bit 2 in hardware serial mode
61 WR/BURST input Multifunctional logic input: write control in software parallel/byte modes or burst mode enable in hardware mode
62 SCLK/RD input Multifunctional logic input: serial clock in serial mode or read control in parallel/byte modes; enables output bus when low with CS
63 CS input Active low chip select logic input; controls three-state output drivers on data lines
64 CHSEL0 input Logic input for channel selection or hardware sequencer programming; read during CONVST or reset
65 CHSEL1 input Logic input for channel selection or hardware sequencer programming; read during CONVST or reset
66 CHSEL2 input Logic input for channel selection or hardware sequencer programming; read during CONVST or reset
67 BUSY output Logic output indicating ongoing analog-to-digital conversion; high during conversion, low when complete
68 CONVST input Logic input to initiate conversion of selected channels when BUSY is low; rising edge triggers start of conversion
69 REGGND power_in Internal analog regulator ground pin; connect to AGND plane with shortest trace
70 REGCAP power_out Internal analog regulator voltage output; decoupled with 10µF ceramic capacitor to REGGND near the pin
71 AVDD power_in Analog power pin 4.75V to 5.25V; connect to nearest AGND with 10µF and 0.1µF decoupling capacitors
72 AGND power_in Analog ground pin; connect all AGND pins to analog ground plane
73 AIN_0B input Analog input channel 0B positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
74 AIN_0BGND input Analog input channel 0B negative input; 0.3V differential range to AIN_0B
75 AIN_1B input Analog input channel 1B positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
76 AIN_1BGND input Analog input channel 1B negative input; 0.3V differential range to AIN_1B
77 AIN_2B input Analog input channel 2B positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
78 AIN_2BGND input Analog input channel 2B negative input; 0.3V differential range to AIN_2B
79 AIN_3B input Analog input channel 3B positive input; accepts ±10V, ±5V, or ±2.5V bipolar signals
80 AIN_3BGND input Analog input channel 3B negative input; 0.3V differential range to AIN_3B

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(14x14)
Category Data Acquisition
Pins 80

CAD (KiCad official)

  • Symbol: ADS8686SIPZAR
  • Footprint: Package_QFP:LQFP-80_14x14mm_P0.65mm
  • 3D model: LQFP-80(14x14) (KiCad packages3D, STEP)
  • 3D model files: ads8686sipzar-etched.step / ads8686sipzar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8686sipzar.step / ads8686sipzar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (117 pp, sha256 ed56e671a196fe1f, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF