component
STM32H562VGT6
Public Made by Adomby adom
ST(意法半导体) , LQFP-100(14x14). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownSTM32H562VGT6
ST(意法半导体) · IC · LQFP-100(14x14)
STM32H562VGT6 from ST(意法半导体), in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACECLK, SPI4_SCK, USART10_RX and FMC_A23. |
| 2 | PE3 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED0, TIM15_BKIN, USART10_TX and FMC_A19, additional function TAMP_IN6/TAMP_OUT3. |
| 3 | PE4 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED1, SPI4_NSS, SAI1_FS_A and FMC_A20, additional function TAMP_IN7/TAMP_OUT8. |
| 4 | PE5 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED2, SPI4_MISO, SAI1_SCK_A and FMC_A21, additional function TAMP_IN8/TAMP_OUT7. |
| 5 | PE6 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED3, TIM1_BKIN2, SPI4_MOSI and FMC_A22, additional function TAMP_IN3/TAMP_OUT6. |
| 6 | VBAT | power_in | Backup-domain supply for the RTC and the 32 backup registers (VBAT mode). |
| 7 | PC13 | bidirectional | 5 V-tolerant FT_t I/O with tamper function in VBAT mode, supplied through the power switch, so output speed must not exceed 2 MHz with a 30 pF load and it must not be used as a current source such as an LED driver. |
| 8 | PC14-OSC32_IN | bidirectional | 5 V-tolerant I/O supplied through the power switch (2 MHz / 30 pF output limit, no current sourcing), also the LSE oscillator input OSC32_IN. |
| 9 | PC15-OSC32_OUT | bidirectional | 5 V-tolerant I/O supplied through the power switch (2 MHz / 30 pF output limit, no current sourcing), also the LSE oscillator output OSC32_OUT. |
| 10 | VSS | power_in | Ground reference of the digital domain; all voltages are referenced to VSS. |
| 11 | VDD | power_in | Standard operating supply voltage of 1.71 to 3.6 V with HSLV = 0, or 1.71 to 2.7 V with HSLV = 1. |
| 12 | PH0-OSC_IN | bidirectional | 5 V-tolerant I/O (FT), also the HSE oscillator input OSC_IN for the 4-50 MHz external oscillator. |
| 13 | PH1-OSC_OUT | bidirectional | 5 V-tolerant I/O (FT), also the HSE oscillator output OSC_OUT for the 4-50 MHz external oscillator. |
| 14 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| 15 | PC0 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions include TIM16_BKIN, SAI1_MCLK_A and FMC_A25, additional function ADC12_INP10. |
| 16 | PC1 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TRACED0, SAI1_SD_A and ETH_MDC, additional functions ADC12_INP11/ADC12_INN10, TAMP_IN3/TAMP_OUT5 and WKUP6. |
| 17 | PC2 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions include PWR_CSLEEP, TIM17_CH1 and ETH_MII_TXD2, additional functions ADC12_INP12/ADC12_INN11. |
| 18 | PC3 | bidirectional | 5 V-tolerant I/O with analog switch supplied by VDDA (FT_a); alternate functions include PWR_CSTOP, SAI1_D3 and OCTOSPI1_IO6, additional functions ADC12_INP13/ADC12_INN12. |
| 19 | VSSA | power_in | Analog ground for the analog domain (ADC, DAC and voltage reference). |
| 20 | VREF- | power_in | Negative voltage reference input for the ADC. |
| 21 | VREF+ | power_in | Positive voltage reference input for the ADC; decoupling with VREF+ connected or not connected to VDDA is shown in Figures 58 and 59. |
| 22 | VDDA | power_in | Analog domain supply, decoupled as shown in the power supply scheme (Figures 20 and 21). |
| 23 | PA0 | bidirectional | 5 V-tolerant I/O with analog switch (FT_at); alternate functions include TIM2_CH1, SPI6_NSS and USART2_CTS/USART2_NSS, additional functions ADC12_INP0, TAMP_IN2/TAMP_OUT1 and WKUP1, with tamper input functional in Standby and VBAT mode. |
| 24 | PA1 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_aht); alternate functions include TIM2_CH2, LPTIM1_IN1 and USART2_RTS/USART2_DE, additional functions ADC12_INP1 and TAMP_IN5/TAMP_OUT4. |
| 25 | PA2 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_hat); alternate functions include TIM2_CH3, LPTIM1_IN2, USART2_TX and ETH_MDIO, additional functions ADC12_INP14, TAMP_IN4/TAMP_OUT3 and WKUP2. |
| 26 | PA3 | bidirectional | 5 V-tolerant I/O with analog switch (FT_ah); alternate functions include TIM2_CH4, OCTOSPI1_CLK, TIM15_CH2 and USART2_RX, additional function ADC12_INP15. |
| 27 | VSS | power_in | Ground reference of the digital domain; all voltages are referenced to VSS. |
| 28 | VDD | power_in | Standard operating supply voltage of 1.71 to 3.6 V with HSLV = 0, or 1.71 to 2.7 V with HSLV = 1. |
| 29 | PA4 | bidirectional | 3.6 V-tolerant I/O with analog switch (TT_a); alternate functions include TIM5_ETR, SPI1_NSS/I2S1_WS and USART2_CK, additional functions ADC12_INP18 and DAC1_OUT1. |
| 30 | PA5 | bidirectional | 3.6 V-tolerant I/O with analog switch and HSLV option (TT_ah); alternate functions include TIM2_CH1, SPI1_SCK/I2S1_CK and ETH_MII_TX_EN/ETH_RMII_TX_EN, additional functions ADC12_INP19, ADC12_INN18 and DAC1_OUT2. |
| 31 | PA6 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TIM1_BKIN, TIM3_CH1, SPI1_MISO/I2S1_SDI and OCTOSPI1_IO3, additional function ADC12_INP3. |
| 32 | PA7 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TIM1_CH1N, TIM3_CH2, SPI1_MOSI/I2S1_SDO and OCTOSPI1_IO2, additional functions ADC12_INP7 and ADC12_INN3. |
| 33 | PC4 | bidirectional | 5 V-tolerant I/O with analog switch (FT_a); alternate functions include TIM2_CH4, SAI1_CK1, LPTIM2_ETR and USART3_RX, additional function ADC12_INP4. |
| 34 | PC5 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TIM1_CH4N, SAI1_D3 and UART12_RTS/UART12_DE, additional functions ADC12_INP8 and ADC12_INN4. |
| 35 | PB0 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TIM1_CH2N, TIM3_CH3, OCTOSPI1_IO1 and USART11_CK, additional functions ADC12_INP9 and ADC12_INN5. |
| 36 | PB1 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TIM1_CH3N, TIM3_CH4, OCTOSPI1_IO0 and LPTIM3_CH2, additional function ADC12_INP5. |
| 37 | PB2 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include RTC_OUT2, SAI1_D1, SPI1_RDY, LPTIM1_CH1 and OCTOSPI1_CLK, additional function LSCO. |
| 38 | PE7 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TIM1_ETR, UART7_RX, OCTOSPI1_IO4 and FMC_D4/FMC_AD4. |
| 39 | PE8 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TIM1_CH1N, UART7_TX, OCTOSPI1_IO5 and FMC_D5/FMC_AD5. |
| 40 | PE9 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TIM1_CH1, UART7_RTS/UART7_DE, OCTOSPI1_IO6 and FMC_D6/FMC_AD6. |
| 41 | PE10 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TIM1_CH2N, UART7_CTS, OCTOSPI1_IO7 and FMC_D7/FMC_AD7. |
| 42 | PE11 | bidirectional | 5 V-tolerant I/O with analog switch and HSLV option (FT_ah); alternate functions include TIM1_CH2, SPI4_NSS, OCTOSPI1_NCS and FMC_D8/FMC_AD8. |
| 43 | PE12 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM1_CH3N, SPI4_SCK, SAI2_SCK_B and FMC_D9/FMC_AD9. |
| 44 | PE13 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM1_CH3, SPI4_MISO, SAI2_FS_B and FMC_D10/FMC_AD10. |
| 45 | PE14 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B and FMC_D11/FMC_AD11. |
| 46 | PE15 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM1_BKIN, TIM1_CH4N, USART10_CK and FMC_D12/FMC_AD12. |
| 47 | PB10 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f); alternate functions include TIM2_CH3, LPTIM3_CH1, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX and OCTOSPI1_NCS. |
| 48 | VCAP | power_out | Connect an external capacitor CEXT to this VCAP pin for the embedded LDO regulator; two VCAP pins must be connected on this package. |
| 49 | VSS | power_in | Ground reference of the digital domain; all voltages are referenced to VSS. |
| 50 | VDD | power_in | Standard operating supply voltage of 1.71 to 3.6 V with HSLV = 0, or 1.71 to 2.7 V with HSLV = 1. |
| 51 | PB12 | bidirectional | 5 V-tolerant Fm+-capable I/O with high-speed low-voltage option (FT_fh); alternate functions include TIM1_BKIN, OCTOSPI1_NCLK, I2C2_SDA, SPI2_NSS/I2S2_WS, UCPD1_FRSTX, USART3_CK, FDCAN2_RX and UART5_RX. |
| 52 | PB13 | bidirectional | USB Type-C power-delivery capable I/O (FT_c, input up to 5.5 V, output timing per Table 67); alternate functions include TIM1_CH1N, LPTIM3_IN1, I2C2_SMBA, SPI2_SCK/I2S2_CK, USART3_CTS/USART3_NSS and FDCAN2_TX, additional function UCPD1_CC1. |
| 53 | PB14 | bidirectional | USB Type-C power-delivery capable I/O (FT_c, input up to 5.5 V, output timing per Table 67); alternate functions include TIM1_CH2N, TIM12_CH1, USART1_TX, SPI2_MISO/I2S2_SDI, USART3_RTS/USART3_DE and SDMMC2_D0, additional function UCPD1_CC2. |
| 54 | PB15 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM1_CH3N, TIM12_CH2, USART1_RX, SPI2_MOSI/I2S2_SDO, SDMMC2_D1 and UART5_RX, additional function PVD_IN. |
| 55 | PD8 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include USART3_TX and FMC_D13/FMC_AD13. |
| 56 | PD9 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include USART3_RX, FDCAN2_RX and FMC_D14/FMC_AD14. |
| 57 | PD10 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include LPTIM2_CH2, USART3_CK and FMC_D15/FMC_AD15. |
| 58 | PD11 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include SAI1_CK1, LPTIM2_IN2, USART3_CTS/USART3_NSS, UART4_RX, OCTOSPI1_IO0 and FMC_A16/FMC_CLE. |
| 59 | PD12 | bidirectional | 5 V-tolerant Fm+-capable I/O with high-speed low-voltage option (FT_fh); alternate functions include LPTIM1_IN1, TIM4_CH1, I2C4_SCL, I3C1_SCL, USART3_RTS/USART3_DE, FMC_A17/FMC_ALE and DCMI_D12/PSSI_D12. |
| 60 | PD13 | bidirectional | 5 V-tolerant Fm+-capable I/O with high-speed low-voltage option (FT_fh); alternate functions include LPTIM1_CH1, TIM4_CH2, I2C4_SDA, I3C1_SDA, OCTOSPI1_IO3, FMC_A18 and DCMI_D13/PSSI_D13. |
| 61 | PD14 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM4_CH3, UART8_CTS, UART9_RX and FMC_D0/FMC_AD0. |
| 62 | PD15 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM4_CH4, UART8_RTS/UART8_DE, UART9_TX and FMC_D1/FMC_AD1. |
| 63 | PC6 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM3_CH1, TIM8_CH1, I2S2_MCK, SAI1_SCK_A, USART6_TX, FMC_NWAIT and DCMI_D0/PSSI_D0. |
| 64 | PC7 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRGIO, TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, FMC_NE1 and DCMI_D1/PSSI_D1. |
| 65 | PC8 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/UART5_DE, FMC_NE2/FMC_NCE and DCMI_D2/PSSI_D2. |
| 66 | PC9 | bidirectional | 5 V-tolerant Fm+-capable I/O with high-speed low-voltage option (FT_fh); alternate functions include MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, AUDIOCLK, UART5_CTS, FMC_CLE and DCMI_D3/PSSI_D3, additional function UCPD1_DB2. |
| 67 | PA8 | bidirectional | 5 V-tolerant Fm+-capable I/O with high-speed low-voltage option (FT_fh); alternate functions include MCO1, TIM1_CH1, I2C3_SCL, SPI1_RDY, USART1_CK, USB_SOF, UART7_RX, FMC_NOE and DCMI_D3/PSSI_D3. |
| 68 | PA9 | bidirectional | 5 V-tolerant I/O with USB Type-C dead-battery function (FT_d); alternate functions include TIM1_CH2, LPUART1_TX, SPI2_SCK/I2S2_CK, USART1_TX and FMC_NWE, additional function UCPD1_DB1. |
| 69 | PA10 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM1_CH3, LPUART1_RX, LPTIM2_IN2, UCPD1_FRSTX, USART1_RX, FDCAN2_TX, SDMMC1_D0 and DCMI_D1/PSSI_D1. |
| 70 | PA11 | bidirectional | 5 V-tolerant I/O with USB function supplied by VDDUSB (FT_u); alternate functions include TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_NSS, FDCAN1_RX and USB_DM. |
| 71 | PA12 | bidirectional | 5 V-tolerant I/O with USB function supplied by VDDUSB (FT_u); alternate functions include TIM1_ETR, LPUART1_RTS/LPUART1_DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/USART1_DE, SAI2_FS_B, FDCAN1_TX and USB_DP. |
| 72 | PA13 (JTMS/SWDIO) | bidirectional | 5 V-tolerant I/O that after reset is the JTMS/SWDIO debug function, with internal pull-up enabled (note 7). |
| 73 | VDDUSB | power_in | Supply for the USB full-speed I/Os (VDDUSB). |
| 74 | VSS | power_in | Ground reference of the digital domain; all voltages are referenced to VSS. |
| 75 | VDD | power_in | Standard operating supply voltage of 1.71 to 3.6 V with HSLV = 0, or 1.71 to 2.7 V with HSLV = 1. |
| 76 | PA14 (JTCK/SWCLK) | bidirectional | 5 V-tolerant I/O that after reset is the JTCK/SWCLK debug function, with internal pull-down enabled (note 7). |
| 77 | PA15 | bidirectional | 5 V-tolerant I/O that after reset is the JTDI debug function, with internal pull-up enabled (note 7); alternate functions include TIM2_CH1, SPI1_NSS/I2S1_WS and SPI3_NSS/I2S3_WS. |
| 78 | PC10 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include LPTIM3_ETR, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, OCTOSPI1_IO1, SDMMC1_D2 and DCMI_D8/PSSI_D8. |
| 79 | PC11 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include LPTIM3_IN1, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, OCTOSPI1_NCS, SDMMC1_D3 and DCMI_D4/PSSI_D4. |
| 80 | PC12 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED3, TIM15_CH1, SPI6_SCK, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK and DCMI_D9/PSSI_D9. |
| 81 | PD0 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM8_CH4N, UART4_RX, FDCAN1_RX, UART9_CTS and FMC_D2/FMC_AD2. |
| 82 | PD1 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include UART4_TX, FDCAN1_TX and FMC_D3/FMC_AD3. |
| 83 | PD2 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TRACED2, TIM3_ETR, TIM15_BKIN, UART5_RX, SDMMC1_CMD, DCMI_D11/PSSI_D11 and LPTIM4_ETR, additional function WKUP7. |
| 84 | PD3 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include SPI2_SCK/I2S2_CK, USART2_CTS/USART2_NSS, FMC_CLK and DCMI_D5/PSSI_D5, additional function WKUP8. |
| 85 | PD4 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include USART2_RTS/USART2_DE, OCTOSPI1_IO4 and FMC_NOE. |
| 86 | PD5 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM1_CH4N, SPI2_RDY, USART2_TX, FDCAN1_TX, OCTOSPI1_IO5 and FMC_NWE. |
| 87 | PD6 | bidirectional | 5 V-tolerant I/O typed as supplied only by VDDIO2 (FT_sh, high-speed low-voltage option); alternate functions include SAI1_D1, SPI3_MOSI/I2S3_SDO, USART2_RX, OCTOSPI1_IO6, SDMMC2_CK and FMC_NWAIT. |
| 88 | PD7 | bidirectional | 5 V-tolerant I/O typed as supplied only by VDDIO2 (FT_sh, high-speed low-voltage option); alternate functions include SPI1_MOSI/I2S1_SDO, USART2_CK, OCTOSPI1_IO7, SDMMC2_CMD, FMC_NE1/FMC_NCE and LPTIM4_OUT. |
| 89 | PB3 (JTDO/TRACESWO) | bidirectional | 5 V-tolerant Fm+-capable I/O with high-speed low-voltage option (FT_fh); alternate functions include TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK and SDMMC2_D2. |
| 90 | PB4(NJTRST) | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h) that after reset is the NJTRST debug function, with internal pull-up enabled (note 7); alternate functions include TIM16_BKIN, TIM3_CH1, OCTOSPI1_CLK and SPI1_MISO/I2S1_SDI. |
| 91 | PB5 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include TIM17_BKIN, TIM3_CH2, OCTOSPI1_NCLK, SPI1_MOSI/I2S1_SDO, FDCAN2_RX, FMC_SDCKE1 and DCMI_D10/PSSI_D10. |
| 92 | PB6 | bidirectional | 5 V-tolerant Fm+-capable I/O (FT_f); alternate functions include TIM16_CH1N, TIM4_CH1, I3C1_SCL, I2C1_SCL, HDMI_CEC, USART1_TX, LPUART1_TX, FDCAN2_TX and FMC_SDNE1. |
| 93 | PB7 | bidirectional | 5 V-tolerant Fm+-capable I/O with analog switch (FT_fa); alternate functions include TIM17_CH1N, TIM4_CH2, I3C1_SDA, I2C1_SDA, USART1_RX, LPUART1_RX and FDCAN1_TX, additional function WKUP5. |
| 94 | BOOT0 | input | Input-only (B structure) boot-mode selection pin; the boot modes depend on TZEN and are listed in Tables 3 and 4. |
| 95 | PB8 | bidirectional | 5 V-tolerant Fm+-capable I/O with high-speed low-voltage option, typed as supplied only by VDDIO2 (FT_fhs); alternate functions include TIM16_CH1, TIM4_CH3, I3C1_SCL, I2C1_SCL, I2C4_SCL, UART4_RX and FDCAN1_RX. |
| 96 | PB9 | bidirectional | 5 V-tolerant Fm+-capable I/O with high-speed low-voltage option, typed as supplied only by VDDIO2 (FT_fhs); alternate functions include TIM17_CH1, TIM4_CH4, I3C1_SDA, I2C1_SDA, SPI2_NSS/I2S2_WS, UART4_TX and FDCAN1_TX. |
| 97 | PE0 | bidirectional | 5 V-tolerant I/O with high-speed low-voltage option (FT_h); alternate functions include LPTIM1_ETR, TIM4_ETR, LPTIM2_CH2, SPI3_RDY, UART8_RX, FDCAN1_RX and FMC_NBL0, additional function DCMI_D2/PSSI_D2 (AF list). |
| 98 | VCAP | power_out | Connect an external capacitor CEXT to this VCAP pin for the embedded LDO regulator; two VCAP pins must be connected on this package. |
| 99 | VSS | power_in | Ground reference of the digital domain; all voltages are referenced to VSS. |
| 100 | VDD | power_in | Standard operating supply voltage of 1.71 to 3.6 V with HSLV = 0, or 1.71 to 2.7 V with HSLV = 1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ST(意法半导体) |
| Package | LQFP-100(14x14) |
| Category | |
| Pins | 100 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External main supply voltage (VDDx - VSS; incl. VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT, VREF+) | VDDx - VSS | -0.3 | 4 | V | 124 | ||
| I/O supply when HSLV = 0 | VDDIOx - VSS | -0.3 | 4 | V | HSLV = 0 | 124 | |
| I/O supply when HSLV = 1 | VDDIOx - VSS | -0.3 | 2.75 | V | HSLV = 1 | 124 | |
| Input voltage on TT_xx pins | VIN | 4 | V | 124 | |||
| Input voltage on FT_c pins | VIN | 5.5 | V | 124 | |||
| Input voltage on any other pins | VIN | 4 | V | 124 | |||
| Allowed voltage difference for VREF+ > VDDA | VREF+-VDDA | 0.4 | V | VREF+ > VDDA | 124 | ||
| Variations between different VDDX power pins of the same domain | /ΔVDDx/ | 50 | mV | 124 | |||
| Variations between all the different ground pins | /VSSx-VSS/ | 50 | mV | 124 | |||
| Total current into sum of all VDD power lines (source) | ∑IVDD | 350 | mA | 125 | |||
| Total current out of sum of all VSS ground lines (sink) | ∑IVSS | 350 | mA | 125 | |||
| Maximum current into each VDD power pin (source) | IVDD | 100 | mA | 125 | |||
| Maximum current out of each VSS ground pin (sink) | IVSS | 100 | mA | 125 | |||
| Output current sunk/sourced by any I/O and control pin | IIO(PIN) | 20 | mA | 125 | |||
| Total output current sunk by sum of all I/Os and control pins | ∑IIO(PIN) | 140 | mA | 125 | |||
| Total output current sourced by sum of all I/Os and control pins | ∑IIO(PIN) | 140 | mA | 125 | |||
| Injected current on FT_xxx, TT_xx, NRST pins | IINJ(PIN) | -5 | 0 | mA | 125 | ||
| Total injected current (sum of all I/Os and control pins) | ∑/IINJ(PIN)/ | -25 | 25 | mA | 125 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 125 | ||
| Maximum junction temperature | TJ | 130 | °C | 125 | |||
| Standard operating voltage | VDD | 1.71 | 3.6 | V | HSLV = 0 | 125 | |
| Standard operating voltage | VDD | 1.71 | 2.7 | V | HSLV = 1 | 125 | |
| I/Os supply voltage (at least one I/O in PB8, PB9, PD6, PD7, PG[9:14] used) | VDDIO2 | 1.08 | 3.6 | V | HSLV = 0 | 126 | |
| I/Os supply voltage (at least one I/O in PB8, PB9, PD6, PD7, PG[9:14] used) | VDDIO2 | 1.08 | 2.7 | V | HSLV = 1 | 126 | |
| I/Os supply voltage (PB8, PB9, PD6, PD7, PG[9:14] not used) | VDDIO2 | 0 | 3.6 | V | PB8, PB9, PD6, PD7, PG[9:14] are not used | 126 | |
| USB supply voltage | VDDUSB | 3 | 3.6 | V | USB is used | 126 | |
| USB supply voltage | VDDUSB | 0 | 3.6 | V | USB is not used | 126 | |
| Analog supply voltage | VDDA | 1.62 | 3.6 | V | ADC is used | 126 | |
| Analog supply voltage | VDDA | 1.8 | V | DAC is used | 126 | ||
| Analog supply voltage | VDDA | 2.1 | V | VREFBUF is used | 126 | ||
| Analog supply voltage | VDDA | 0 | V | ADC, DAC, and VREFBUF are not used | 126 | ||
| Backup domain supply voltage | VBAT | 1.2 | 3.6 | V | 126 | ||
| I/O input voltage (all I/Os except FT_c and TT_xx) | VIN | -0.3 | V | All I/Os except FT_c and TT_xx | 126 | ||
| I/O input voltage (FT_c I/O) | VIN | -0.3 | 5 | V | FT_c I/O | 126 | |
| I/O input voltage (TT_xx I/O) | VIN | -0.3 | V | TT_xx I/O | 126 | ||
| Internal regulator ON, VCORE | VCORE | 1.3 | 1.35 | 1.4 | V | VOS0 (max frequency for AHB and APB: 250 MHz) | 127 |
| Internal regulator ON, VCORE | VCORE | 1.15 | 1.2 | 1.26 | V | VOS1 (max frequency for AHB and APB: 200 MHz) | 127 |
| Internal regulator ON, VCORE | VCORE | 1.05 | 1.1 | 1.15 | V | VOS2 (max frequency for AHB and APB: 150 MHz) | 127 |
| Internal regulator ON, VCORE | VCORE | 0.95 | 1 | 1.05 | V | VOS3 (max frequency for AHB and APB: 100 MHz) | 127 |
| Regulator OFF, external VCORE | VCORE | 1.32 | 1.35 | 1.4 | V | VOS0 | 127 |
| Regulator OFF, external VCORE | VCORE | 1.17 | 1.2 | 1.26 | V | VOS1 | 127 |
| Regulator OFF, external VCORE | VCORE | 1.07 | 1.1 | 1.15 | V | VOS2 | 127 |
| Regulator OFF, external VCORE | VCORE | 0.97 | 1 | 1.05 | V | VOS3 | 127 |
| AHB clock frequency | fHCLK | 250 | MHz | VOS0 | 127 | ||
| AHB clock frequency | fHCLK | 200 | MHz | VOS1 | 127 | ||
| AHB clock frequency | fHCLK | 150 | MHz | VOS2 | 127 | ||
| AHB clock frequency | fHCLK | 100 | MHz | VOS3 | 127 | ||
| Ambient temperature for the suffix 6 version (maximum power dissipation) | TA | -40 | 85 | °C | Maximum power dissipation | 128 | |
| Junction temperature range | TJ | -40 | 105 | °C | VOS0 | 128 | |
| Junction temperature range | TJ | -40 | 130 | °C | VOS1, VOS2, and VOS3 | 128 | |
| External capacitor for LDO enabled | CEXT | 2.2 | µF | LDO enabled | 130 | ||
| Tolerance of CEXT | CEXT | -20 | 20 | % | Variation tolerated | 130 | |
| Equivalent series resistance of the external capacitor | ESR | 100 | mΩ | 130 | |||
| Reset temporization after BOR0 detection | tRSTTEMPO | 377 | 550 | μs | VDD rising | 133 | |
| Power-on/down reset threshold (BORH_EN = 0), rising edge | VPOR/PDR | 1.62 | 1.67 | 1.71 | V | Rising edge | 133 |
| Power-on/down reset threshold (BORH_EN = 0), falling edge | VPOR/PDR | 1.58 | 1.62 | 1.68 | V | Falling edge | 133 |
| Internal reference voltage | VREFINT | 1.18 | 1.216 | 1.255 | V | -40 °C < TJ < +130 °C | 135 |
| Internal reference voltage spread over the temperature range | ΔVREFINT | 5 | 15 | mV | -40 °C < TJ < +130 °C | 135 | |
| Average temperature coefficient | TCoeff | 20 | 70 | ppm/°C | 135 | ||
| Average voltage coefficient | VDDcoeff | 10 | 1370 | ppm/V | 3.0 V < VDD < 3.6 V | 135 |
CAD (KiCad official)
- Symbol:
STM32H562VGT6 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
stm32h562vgt6-etched.step/stm32h562vgt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32h562vgt6.step/stm32h562vgt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ST(意法半导体) datasheet (270 pp, sha256
fc24f0be69fd186b, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).