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CBM53D14BMS
Public Made by Adomby adom
Corebai Microelectronics Analog To Digital Converters (ADCs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCBM53D14BMS
Corebai Microelectronics · Analog To Digital Converters (ADCs) · MSOP-10
CBM53D14BMS from Corebai Microelectronics, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input operating from 2.5V to 5.5V, to be decoupled to GND. |
| 2 | VOUTA | output | Buffered analog output voltage from DAC A with rail-to-rail output amplifier. |
| 3 | VOUTB | output | Buffered analog output voltage from DAC B with rail-to-rail output amplifier. |
| 4 | VOUTC | output | Buffered analog output voltage from DAC C with rail-to-rail output amplifier. |
| 5 | Refin | input | Reference input pin for all four DACs with an input range from 0.25V to VDD. |
| 6 | VOUTD | output | Buffered analog output voltage from DAC D with rail-to-rail output amplifier. |
| 7 | GND | power_in | Ground reference point for all circuitry on the part. |
| 8 | Din | input | Serial data input to the 16-bit shift register, clocked in on the falling edge of Sclk; the input buffer is powered down after each write cycle. |
| 9 | Sclk | input | Serial clock input, data is clocked in on the falling edge at clock speeds up to 30MHz; the input buffer is powered down after each write cycle. |
| 10 | Sync | input | Active-low frame synchronization input that enables the input shift register for 16 falling Sclk edges; taking it high before the 16th falling edge aborts the write. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Corebai Microelectronics |
| Package | MSOP-10 |
| Category | Data Converters |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply | VDD | 2.5 | 5.5 | V | 3 | ||
| Ambient Temperature | Ta | -40 | 105 | ℃ | 3 | ||
| VDD to GND | VDDabs | -0.3 | 7 | V | TA=25℃ | 3 | |
| Operating Temperature Range Industrial | -40 | 105 | ℃ | 3 | |||
| Storage Temperature Range | TS | -65 | 150 | ℃ | 3 | ||
| Junction Temperature | TJmax | 150 | ℃ | 3 | |||
| Resolution | ResN | 10 | Bits | CBM53D14 | 4 | ||
| Relative Accuracy | INL | -0.5 | 0.5 | LSB | CBM53D14; VDD=2.5V to 5.5V; VREF=2V; RL=2KΩ; CL=200pF; Ta=25℃ | 4 | |
| Differential Nonlinearity | DNL | -0.05 | 0.05 | LSB | CBM53D14; Monotonic Guaranteed | 4 | |
| Offset Error | -0.4 | 0.4 | %of FSR | 4 | |||
| Gain Error | -0.15 | 0.15 | %of FSR | 4 | |||
| VREF Input Range | 0.25 | 5.5 | V | 0.25 to VDD | 4 | ||
| Input Low Voltage | VIL | 0.6 | V | VDD=3V | 4 | ||
| Input High Voltage | VIH | 2.1 | V | VDD=3V | 5 | ||
| Power supply | VDD | 2.5 | 5.5 | V | 5 | ||
| IDD (Normal Mode) | IDD | 600 | uA | VDD=4.5V to 5.5V; VIH=VDD and VIL=GND | 5 | ||
| IDD (Normal Mode) | IDD | 500 | uA | VDD=2.5V to 3.6V; VIH=VDD and VIL=GND | 5 | ||
| IDD (Power-Down Mode) | IDD | 0.2 | uA | VDD=4.5V to 5.5V; VIH=VDD and VIL=GND | 5 | ||
| IDD (Power-Down Mode) | IDD | 0.08 | uA | VDD=2.5V to 3.6V; VIH=VDD and VIL=GND | 5 | ||
| Output Voltage Setting Time | 7 | uS | CBM53D14; 1/4 scale to 3/4 scale change (0x100 to 0x300) | 5 | |||
| Slew Rate | 0.7 | V/uS | 5 | ||||
| SCLK cycle time t1 | t1 | 40 | ns | VDD=2.5V to 3.6V | 6 | ||
| SCLK cycle time t1 | t1 | 33 | ns | VDD=3.6V to 5.5V | 6 | ||
| SCLK high time t2 | t2 | 16 | ns | VDD=2.5V to 3.6V | 6 | ||
| SCLK high time t2 | t2 | 13 | ns | VDD=3.6V to 5.5V | 6 | ||
| SCLK low time t3 | t3 | 16 | ns | VDD=2.5V to 3.6V | 6 | ||
| SCLK low time t3 | t3 | 13 | ns | VDD=3.6V to 5.5V | 6 | ||
| SYNC to SCLK falling edge setup time t4 | t4 | 16 | ns | VDD=2.5V to 3.6V | 6 | ||
| SYNC to SCLK falling edge setup time t4 | t4 | 13 | ns | VDD=3.6V to 5.5V | 6 | ||
| Data setup time t5 | t5 | 5 | ns | VDD=2.5V to 5.5V | 6 | ||
| Data hold time t6 | t6 | 4.5 | ns | VDD=2.5V to 5.5V | 6 | ||
| SCLK falling edge to SYNC rising edge t7 | t7 | 0 | ns | VDD=2.5V to 5.5V | 6 | ||
| Minimum SYNC high time t8 | t8 | 80 | ns | VDD=2.5V to 3.6V | 6 | ||
| Minimum SYNC high time t8 | t8 | 33 | ns | VDD=3.6V to 5.5V | 6 | ||
| Major-Code Transition Glitch Energy | 40 | nV-sec | 1 LSB change around major carry | 5 | |||
| Multiplying Bandwidth | 200 | kHz | VREF=2V±0.1VP-P | 6 | |||
| Total Harmonic Distortion | -70 | dB | VREF=2.5V±0.1VP-P; Frequency=10KHz | 6 |
CAD (KiCad official)
- Symbol:
CBM53D14BMS - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
cbm53d14bms-etched.step/cbm53d14bms-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cbm53d14bms.step/cbm53d14bms.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Corebai Microelectronics datasheet (18 pp, sha256
664b142b3a67084b, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).