component
TPS62A03DRLR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS62A03DRLR
Texas Instruments · DC-DC Converters · SOT-563
TPS62A03DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin, and the low side of the input and output capacitors should connect to it to avoid a ground potential shift. |
| 2 | SW | output | Switch pin connected to the internal FET switches and the inductor terminal, with DC limits of -0.3 V to VIN + 0.3 V and transients below 10 ns limited to -3.0 V to 10 V. |
| 3 | VIN | power_in | Power supply voltage pin with a recommended input range of 2.5 V to 5.5 V and an absolute maximum of -0.3 V to 6 V. |
| 4 | EN | input | Device enable logic input where logic high enables the device and logic low shuts it down, with VEN(R) 0.8 V and VEN(F) 0.4 V thresholds, an absolute maximum of 6 V, and it must not be left floating. |
| 5 | FB | input | Feedback pin for the internal control loop that connects to an external feedback divider, with an absolute maximum of -0.3 V to 3 V. |
| 6 | PG | output | Power-good open-drain output whose pullup resistor must not connect to any voltage above 5.5 V, with an absolute maximum of 6 V and a low-level output of 400 mV at 1 mA, and it can be left open or tied to GND if unused. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VUVLO rising threshold | VUVLO(R) | 2.3 | 2.4 | 2.5 | V | VIN rising | 5 |
| VUVLO falling threshold | VUVLO(F) | 2.2 | 2.3 | 2.4 | V | VIN falling | 5 |
| EN high-level input voltage | VEN(R) | 0.8 | V | EN rising, enable switching | 5 | ||
| EN low-level input voltage | VEN(F) | 0.4 | V | EN falling, disable switching | 5 | ||
| EN input leakage current | VEN(LKG) | 100 | nA | VEN = 5V | 5 | ||
| FB voltage | VFB | 594 | 600 | 606 | mV | TJ = 0°C to 125°C, PWM mode | 5 |
| FB voltage | VFB | 591 | 600 | 609 | mV | PWM mode | 5 |
| Load dependent output voltage drop (load regulation) | 0.15 | %/A | PWM mode | 5 | |||
| FB input leakage current | IFB(LKG) | 100 | nA | VFB = 0.6V | 5 | ||
| VIN shutdown supply current | ISD(VIN) | 0.15 | 2 | µA | VEN = Low; TJ = -40°C to 85°C | 5 | |
| High-side peak current limit (TPS62A03) | IHS(OC) | 3.9 | 5 | A | TPS62A03; VIN = 3.3V | 5 | |
| VIN quiescent current | IQ(VIN) | 28 | µA | Non-switching, VEN = High, VFB = 610mV | 5 | ||
| Switching frequency, FPWM operation | fSW(FCCM) | 2200 | kHz | VIN = 5V, VOUT = 1.8V | 5 | ||
| Internal fixed soft-start time | 1 | ms | From EN = High to VFB = 0.56V; VOUT = 0.6V; TJ = 0°C to 85°C | 5 | |||
| High-side MOSFET on-resistance | RDSON(HS) | 42 | mΩ | VIN = 5V | 5 | ||
| Low-side MOSFET on-resistance | RDSON(LS) | 28 | mΩ | VIN = 5V | 5 | ||
| Low-side valley current limit (TPS62A03) | ILS(OC) | 4.2 | A | TPS62A03; VIN = 3.3V | 5 | ||
| Peak inductor current in PSM | ILPEAK(min) | 0.5 | A | 5 | |||
| Power Good threshold (falling edge) | VPGTH | 93.5 | % | PG high to low (falling edge), FB falling | 5 | ||
| Power Good threshold (rising edge) | VPGTH | 96 | % | PG low to high (rising edge), FB rising | 5 | ||
| PG delay falling | 35 | µs | 5 | ||||
| PG delay rising | 10 | µs | 5 | ||||
| PG pin leakage current when open drain output is high | IPG(LKG) | 100 | nA | VPG = 5V | 5 | ||
| PG pin output low-level voltage | 400 | mV | IPG = 1mA | 5 | |||
| Output discharge current on SW pin | 120 | mA | VIN = 3V, VOUT = 2.0V | 5 | |||
| Thermal shutdown threshold | TJ(SD) | 165 | °C | Temperature rising | 5 | ||
| Thermal shutdown hysteresis | TJ(HYS) | 20 | °C | 5 | |||
| Input supply voltage range | VIN | 2.5 | 5.5 | V | 4 | ||
| Output voltage range | VOUT | 0.6 | V | 4 | |||
| Output current range (TPS62A03) | IOUT | 3 | A | TPS62A03 | 4 | ||
| Effective inductance | L | 0.3 | 1 | 1.2 | µH | 4 | |
| Output capacitance | COUT | 44 | µF | VOUT < 1.2V | 4 | ||
| Output capacitance | COUT | 22 | µF | 1.2V ≤ VOUT < 1.8V | 4 | ||
| Power-Good input current capability | IPG | 0 | 1 | mA | 4 | ||
| Operating junction temperature (recommended) | TJ | -40 | 125 | °C | Over operating junction temperature range | 4 | |
| Power-good pull-up voltage | 5.5 | V | Pull-up resistor on PG pin | 3 | |||
| Feedback divider lower resistor R2 | R2 | 100 | kΩ | To provide acceptable noise sensitivity | 11 | ||
| Pin voltage VIN, EN, PG | -0.3 | 6 | V | 4 | |||
| Pin voltage SW, DC | -0.3 | V | 4 | ||||
| Pin voltage SW, transient | -3 | 10 | V | transient < 10ns | 4 | ||
| Pin voltage FB | -0.3 | 3 | V | 4 | |||
| Operating junction temperature (absolute maximum) | TJ | -40 | 150 | °C | Operating junction temperature | 4 | |
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Electrostatic discharge, human-body model | V(ESD) | -2000 | 2000 | V | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | 4 | |
| Electrostatic discharge, charged-device model | V(ESD) | -500 | 500 | V | Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 | 4 | |
| Junction-to-ambient thermal resistance | RθJA | 157.3 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 92.2 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 45.6 | °C/W | 4 | |||
| Junction-to-top characterization parameter | ψJT | 4 | °C/W | 4 | |||
| Junction-to-board characterization parameter | ψJB | 45 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
TPS62A03DRLR - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files:
tps62a03drlr-etched.step/tps62a03drlr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps62a03drlr.step/tps62a03drlr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
db38a14c2b2dfcfb, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).