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STC15W4K48S4-30I-LQFP64S

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STC Micro Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersstc15w4k48s4-30i-lqfp64sfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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STC15W4K48S4-30I-LQFP64S

STC Micro · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

STC15W4K48S4-30I-LQFP64S from STC Micro, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P5.3 bidirectional Standard I/O port PORT5[3], alternate function TxD4_2 (UART4 transmit).
2 P0.5 bidirectional Standard I/O port PORT0[5], alternate functions AD5 address/data bus, T3 external input of timer 3 and PWMFLT_2 PWM abnormal-stop control.
3 P0.6 bidirectional Standard I/O port PORT0[6], alternate functions AD6 address/data bus, T4CLKO timer 4 clock output and PWM7_2 (high-impedance input after power-up, must be set to another mode by software to drive out).
4 P0.7 bidirectional Standard I/O port PORT0[7], alternate functions AD7 address/data bus, T4 timer 4 external input and PWM6_2 (high-impedance input after power-up, must be set to another mode by software to drive out).
5 P6.0 bidirectional Standard I/O port PORT6[0].
6 P6.1 bidirectional Standard I/O port PORT6[1].
7 P6.2 bidirectional Standard I/O port PORT6[2].
8 P6.3 bidirectional Standard I/O port PORT6[3].
9 P1.0 bidirectional Standard I/O port PORT1[0], alternate functions ADC0 input channel 0, CCP1 capture/high-speed pulse/PWM channel 1 and RxD2 (UART2 receive).
10 P1.1 bidirectional Standard I/O port PORT1[1], alternate functions ADC1 input channel 1, CCP0 capture/high-speed pulse/PWM channel 0 and TxD2 (UART2 transmit).
11 P4.7 bidirectional Standard I/O port PORT4[7], alternate function TxD2_2 (UART2 transmit).
12 P1.2 bidirectional Standard I/O port PORT1[2], alternate functions ADC2 input channel 2, SS SPI slave select, ECI CCP/PCA counter external pulse input and CMPO comparator output.
13 P1.3 bidirectional Standard I/O port PORT1[3], alternate functions ADC3 input channel 3 and SPI MOSI (master out, slave in).
14 P1.4 bidirectional Standard I/O port PORT1[4], alternate functions ADC4 input channel 4 and SPI MISO (master in, slave out).
15 P1.5 bidirectional Standard I/O port PORT1[5], alternate functions ADC5 input channel 5 and SPI SCLK clock.
16 P1.6 bidirectional Standard I/O port PORT1[6], alternate functions ADC6, RxD_3 (UART1 receive), SysClkO_2 system clock output (SysClk/1, /2, /4, /16), XTAL2 crystal oscillator output and PWM6 (high-impedance input after power-up).
17 P1.7 bidirectional Standard I/O port PORT1[7], alternate functions ADC7, TxD_3 (UART1 transmit), XTAL1 crystal/external clock input and PWM7 (high-impedance input after power-up).
18 P5.4 bidirectional Standard I/O port PORT5[4], alternate functions RST reset (active high), SysClkO system clock output (SysClk/1, /2, /4, /16), SS_3 SPI slave select and CMP- comparator negative input (must be set high-impedance when used as CMP-).
19 Vcc power_in Positive power supply.
20 P5.5 bidirectional Standard I/O port PORT5[5], alternate function CMP+ comparator positive input (must be set high-impedance when used as CMP+).
21 Gnd power_in Power negative terminal, ground.
22 P4.0 bidirectional Standard I/O port PORT4[0], alternate function SPI MOSI_3 per pin diagram (the pin table names it MISO_3).
23 P6.4 bidirectional Standard I/O port PORT6[4].
24 P6.5 bidirectional Standard I/O port PORT6[5].
25 P6.6 bidirectional Standard I/O port PORT6[6].
26 P6.7 bidirectional Standard I/O port PORT6[7].
27 P3.0 bidirectional Standard I/O port PORT3[0], alternate functions RxD (UART1 receive), INT4 falling-edge-only external interrupt 4 with power-down wake-up, and T2CLKO timer 2 clock output.
28 P3.1 bidirectional Standard I/O port PORT3[1], alternate functions TxD (UART1 transmit) and T2 timer/counter 2 external input.
29 P3.2 bidirectional Standard I/O port PORT3[2], alternate function INT0 external interrupt 0 (falling edge only if IT0=1, both edges if IT0=0) with power-down wake-up.
30 P3.3 bidirectional Standard I/O port PORT3[3], alternate function INT1 external interrupt 1 (falling edge only if IT1=1, both edges if IT1=0) with power-down wake-up.
31 P3.4 bidirectional Standard I/O port PORT3[4], alternate functions T0 timer 0 external input, T1CLKO timer 1 clock output and ECI_2 CCP/PCA counter external pulse input.
32 P5.0 bidirectional Standard I/O port PORT5[0], alternate function RxD3_2 (UART3 receive).
33 P5.1 bidirectional Standard I/O port PORT5[1], alternate function TxD3_2 (UART3 transmit).
34 P3.5 bidirectional Standard I/O port PORT3[5], alternate functions T1 timer 1 external input, T0CLKO timer 0 clock output and CCP0_2 capture/high-speed pulse/PWM channel 0.
35 P3.6 bidirectional Standard I/O port PORT3[6], alternate functions INT2 falling-edge-only external interrupt 2 with power-down wake-up, RxD_2 (UART1 receive) and CCP1_2 capture/high-speed pulse/PWM channel 1.
36 P3.7 bidirectional Standard I/O port PORT3[7], alternate functions INT3 falling-edge-only external interrupt 3 with power-down wake-up, TxD_2 (UART1 transmit) and PWM2 (high-impedance input after power-up).
37 P7.0 bidirectional Standard I/O port PORT7[0].
38 P7.1 bidirectional Standard I/O port PORT7[1].
39 P7.2 bidirectional Standard I/O port PORT7[2].
40 P7.3 bidirectional Standard I/O port PORT7[3].
41 P4.1 bidirectional Standard I/O port PORT4[1], alternate function SPI MISO_3 per pin diagram (the pin table names it MOSI_3).
42 P4.2 bidirectional Standard I/O port PORT4[2], alternate functions WR external data memory write pulse and PWM5_2 (high-impedance input after power-up).
43 P4.3 bidirectional Standard I/O port PORT4[3], alternate function SCLK_3 SPI clock.
44 P4.4 bidirectional Standard I/O port PORT4[4], alternate functions RD external data memory read pulse and PWM4_2 (high-impedance input after power-up).
45 P2.0 bidirectional Standard I/O port PORT2[0], alternate functions A8 address bit 8 and RSTOUT_LOW (output low after power-up and during reset, software-configurable).
46 P2.1 bidirectional Standard I/O port PORT2[1], alternate functions A9 address bit 9, SCLK_2 SPI clock and PWM3 (high-impedance input after power-up).
47 P2.2 bidirectional Standard I/O port PORT2[2], alternate functions A10 address bit 10, MISO_2 SPI master in/slave out and PWM4 (high-impedance input after power-up).
48 P2.3 bidirectional Standard I/O port PORT2[3], alternate functions A11 address bit 11, MOSI_2 SPI master out/slave in and PWM5 (high-impedance input after power-up).
49 P2.4 bidirectional Standard I/O port PORT2[4], alternate functions A12 address bit 12, ECI_3 CCP/PCA counter external pulse input, SS_2 SPI slave select and PWMFLT PWM abnormal-stop control.
50 P2.5 bidirectional Standard I/O port PORT2[5], alternate functions A13 address bit 13 and CCP0_3 capture/high-speed pulse/PWM channel 0.
51 P2.6 bidirectional Standard I/O port PORT2[6], alternate functions A14 address bit 14 and CCP1_3 capture/high-speed pulse/PWM channel 1.
52 P2.7 bidirectional Standard I/O port PORT2[7], alternate functions A15 address bit 15 and PWM2_2 (high-impedance input after power-up).
53 P7.4 bidirectional Standard I/O port PORT7[4].
54 P7.5 bidirectional Standard I/O port PORT7[5].
55 P7.6 bidirectional Standard I/O port PORT7[6].
56 P7.7 bidirectional Standard I/O port PORT7[7].
57 P4.5 bidirectional Standard I/O port PORT4[5], alternate functions ALE address latch enable and PWM3_2 (high-impedance input after power-up).
58 P4.6 bidirectional Standard I/O port PORT4[6], alternate function RxD2_2 (UART2 receive).
59 P0.0 bidirectional Standard I/O port PORT0[0], alternate functions AD0 address/data bus and RxD3 (UART3 receive).
60 P0.1 bidirectional Standard I/O port PORT0[1], alternate functions AD1 address/data bus and TxD3 (UART3 transmit).
61 P0.2 bidirectional Standard I/O port PORT0[2], alternate functions AD2 address/data bus and RxD4 (UART4 receive).
62 P0.3 bidirectional Standard I/O port PORT0[3], alternate functions AD3 address/data bus and TxD4 (UART4 transmit).
63 P0.4 bidirectional Standard I/O port PORT0[4], alternate functions AD4 address/data bus and T3CLKO timer 3 clock output.
64 P5.2 bidirectional Standard I/O port PORT5[2], alternate function RxD4_2 (UART4 receive).

Key specifications

Parameter Value
Manufacturer STC Micro
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following 441

CAD (KiCad official)

  • Symbol: STC15W4K48S4-30I-LQFP64S
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: stc15w4k48s4-30i-lqfp64s-etched.step / stc15w4k48s4-30i-lqfp64s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stc15w4k48s4-30i-lqfp64s.step / stc15w4k48s4-30i-lqfp64s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STC Micro datasheet (1219 pp, sha256 cc8c299c891646e0, retrieved 2026-10-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF