AD7478AARMZ from Analog Devices, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Power supply input; the VDD range is 2.35 V to 5.25 V and also sets the reference and the 0 V to VDD analog input range.
2	SDATA	output	Serial data output carrying four leading zeros, 8 bits of conversion data MSB first, then four trailing zeros, clocked out on the falling edge of SCLK.
3	CS	input	Active-low chip select that initiates conversions and frames the serial data transfer.
4	NC	unconnected	No connect.
5	NC	unconnected	No connect.
6	SCLK	input	Serial clock input for accessing data from the part, also used as the clock source for the conversion process.
7	GND	power_in	Analog ground reference point for all circuitry; refer all analog input signals to this voltage.
8	VIN	power_in	Single-ended analog input channel with an input range of 0 V to VDD.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	MSOP-8
Category	Data Converters
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDD	VDD	2.35		5.25	V		11
VDD to GND	VDD	-0.3		7	V		10
Analog input voltage to GND		-0.3			V		10
Digital input voltage to GND		-0.3		7	V		10
Digital output voltage to GND		-0.3			V		10
Input current to any pin except supplies				10	mA		10
Operating temperature range (commercial, A grade)		-40		85	°C	Commercial (A and B Grades)	10
Storage temperature range		-65		150	°C		10
Junction temperature				150	°C		10
ESD rating (all other models)				3.5	kV		10
Linearity error (integral nonlinearity), ±0.3 maximum	INL	-0.3		0.3	LSB		27
SCLK frequency, A and B grades	fSCLK	10			kHz	A, B grades	8
SCLK frequency maximum	fSCLK			20	MHz		8
CS pulse width	t1	10			ns		8
CS to SCLK setup time	t2	10			ns		8
Delay from CS until SDATA three-state disabled	t3			22	ns		8
Data access time after SCLK falling edge	t4			40	ns		8
SCLK low pulse width	t5	0.4			tSCLK		8
SCLK high pulse width	t6	0.4			tSCLK		8
SCLK to data valid hold time	t7	10			ns	VDD ≤ 3.3 V	8
SCLK to data valid hold time	t7	9.5			ns	3.3 V < VDD ≤ 3.6 V	8
SCLK to data valid hold time	t7	7			ns	VDD > 3.6 V	8
SCLK falling edge to SDATA high impedance	t8			36	ns		8
Quiet time between bus relinquish and start of next conversion	tQUIET	50			ns		8
Power-up time from full power-down	tPOWER-UP			1	μs		8
Thermal impedance junction to ambient (MSOP)	θJA		205.9		°C/W	MSOP package	10
Thermal impedance junction to case (MSOP)	θJC		43.74		°C/W	MSOP package	10
Lead temperature, reflow soldering			235		°C	Reflow (10 sec to 30 sec)	10
Pb-free temperature soldering, reflow			255		°C	Pb-free reflow	10

CAD (KiCad official)

Symbol: AD7478AARMZ
Footprint: Package_SO:MSOP-8_3x3mm_P0.65mm
3D model: MSOP-8 (KiCad packages3D, STEP)
3D model files: ad7478aarmz-etched.step / ad7478aarmz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7478aarmz.step / ad7478aarmz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 f7084789e08c0a5a, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD7478AARMZ

Verified AD7478AARMZ

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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