component
CD4093BPWR
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4093BPWR
Texas Instruments · Logic Gates · TSSOP-14
CD4093BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Schmitt-trigger input A of NAND gate 1 (J = NAND(A,B)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |
| 2 | B | input | Schmitt-trigger input B of NAND gate 1 (J = NAND(A,B)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |
| 3 | J | output | Output of Schmitt-trigger NAND gate 1, J = NAND(A,B), standardized symmetrical CMOS output stage. |
| 4 | K | output | Output of Schmitt-trigger NAND gate 2, K = NAND(C,D), standardized symmetrical CMOS output stage. |
| 5 | C | input | Schmitt-trigger input C of NAND gate 2 (K = NAND(C,D)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |
| 6 | D | input | Schmitt-trigger input D of NAND gate 2 (K = NAND(C,D)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |
| 7 | VSS | power_in | Negative supply / ground reference terminal; all other voltages, including VDD (−0.5 V to +20 V), are referenced to this pin. |
| 8 | E | input | Schmitt-trigger input E of NAND gate 3 (L = NAND(E,F)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |
| 9 | F | input | Schmitt-trigger input F of NAND gate 3 (L = NAND(E,F)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |
| 10 | L | output | Output of Schmitt-trigger NAND gate 3, L = NAND(E,F), standardized symmetrical CMOS output stage. |
| 11 | M | output | Output of Schmitt-trigger NAND gate 4, M = NAND(G,H), standardized symmetrical CMOS output stage. |
| 12 | G | input | Schmitt-trigger input G of NAND gate 4 (M = NAND(G,H)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |
| 13 | H | input | Schmitt-trigger input H of NAND gate 4 (M = NAND(G,H)); protected by internal CMOS diode network, max input current 1 µA at 18 V over temperature. |
| 14 | VDD | power_in | Positive supply pin; DC supply-voltage range −0.5 V to +20 V referenced to VSS, recommended operating supply range 3 V to 18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4093BPWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4093bpwr-etched.step/cd4093bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4093bpwr.step/cd4093bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
c981171c0409a8a0, retrieved 2026-09-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-5(text+vision), consensusclaude-opus-4-8(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).