AD7714YRUZ-REEL7 from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SCLK	input	Serial clock logic input used to access serial data, which can be a continuous clock or a noncontinuous clock.
2	MCLK IN	input	Master clock input for a crystal/resonator or CMOS-compatible external clock; the part is specified with 1 MHz and 2.4576 MHz clock frequencies.
3	MCLK OUT	output	Crystal/resonator connection to MCLK IN, or an inverted clock output when an external clock drives MCLK IN.
4	POL	input	Clock polarity logic input; low means the first SCLK transition is low to high, high means the first transition is high to low.
5	SYNC	input	Logic input that synchronizes the digital filters and analog modulators of multiple AD7714s; while low it resets the filter nodes, filter and calibration control logic and holds the modulator in reset.
6	RESET	input	Active-low logic input that resets the control logic, interface logic, digital filter and analog modulator to power-on status.
7	AIN1	input	Analog input channel 1, programmable-gain, pseudo-differential with AIN6 or positive input of a differential pair with AIN2.
8	AIN2	input	Analog input channel 2, programmable-gain, pseudo-differential with AIN6 or negative input of a differential pair with AIN1.
9	AIN3	input	Analog input channel 3, programmable-gain, pseudo-differential with AIN6 or positive input of a differential pair with AIN4.
10	AIN4	input	Analog input channel 4, programmable-gain, pseudo-differential with AIN6 or negative input of a differential pair with AIN3.
11	STANDBY	input	Logic input; taking it low shuts down analog and digital circuitry, reducing current consumption to typically 5 µA.
12	AVDD	power_in	Analog positive supply voltage; Y grade versions are 3 V or 5 V nominal.
13	BUFFER	input	Buffer option select input; low shorts out the on-chip analog input buffer (AVDD current reduced to 270 µA), high puts the buffer in series with the input for higher source impedances.
14	REF IN(-)	input	Negative differential reference input, which can lie anywhere between AVDD and AGND provided REF IN(+) is greater than REF IN(-).
15	REF IN(+)	input	Positive differential reference input, which can lie anywhere between AVDD and AGND and must be greater than REF IN(-).
16	AIN5	input	Analog input channel 5, programmable-gain positive input of a differential pair when used with AIN6.
17	AIN6	input	Analog input channel 6, reference point for AIN1 through AIN4 in pseudo-differential mode or negative input of a differential pair with AIN5.
18	AGND	power_in	Ground reference point for analog circuitry.
19	CS	input	Active-low chip select input; can be hard-wired low for three-wire interface mode, or used for device selection or frame synchronization.
20	DRDY	output	Logic output; low indicates a new output word is available in the data register, and it also indicates completion of on-chip calibration.
21	DOUT	tri_state	Serial data output from the output shift register, which can hold calibration, mode, communications, filter or data register contents.
22	DIN	input	Serial data input to the input shift register, with data transferred to the register selected by the Communications Register.
23	DVDD	power_in	Digital supply voltage; Y grade versions are 3 V or 5 V nominal.
24	DGND	power_in	Ground reference point for digital circuitry.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-24
Category	Data Converters
Pins	24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
No Missing Codes		24			Bits	Guaranteed by Design. For Filter Notches ≤ 60 Hz	5
Integral Nonlinearity		-0.001		0.001	% of FSR	Filter Notches ≤ 60 Hz.	5
Bipolar Negative Full-Scale Error (5 V)		-0.0015		0.0015	% of FSR	AVDD = 5 V. Typically ±0.0004%	5
Bipolar Negative Full-Scale Error (3 V)		-0.003		0.003	% of FSR	AVDD = 3 V. Typically ±0.0004%	5
Input Common-Mode Rejection	CMR	90	102		dB	At DC. Typically 102 dB.	5
Normal-Mode 50 Hz Rejection		100			dB	For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × fNOTCH	5
Normal-Mode 60 Hz Rejection		100			dB	For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 × fNOTCH	5
Common-Mode 50 Hz Rejection		150			dB	For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 × fNOTCH	5
Common-Mode 60 Hz Rejection		150			dB	For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 × fNOTCH	5
AIN DC Input Current				1	nA		5
AIN Sampling Capacitance				7	pF		5
REF IN(+), REF IN(-) Voltage (3 V)	VREF	1		1.75	V	AVDD = 2.7 V to 3.3 V. VREF = 1.25 ±1% for Specified Performance	5
REF IN(+), REF IN(-) Voltage (5 V)	VREF	1		3.5	V	AVDD = 4.75 V to 5.25 V. VREF = 2.5 ±1% for Specified Performance	5
Logic Input Current		-10		10	µA	All Inputs Except MCLK IN	5
Input Low Voltage (DVDD = 5 V)	VINL			0.8	V	DVDD = 5 V. All Inputs Except MCLK IN	5
Input Low Voltage (DVDD = 3 V)	VINL			0.4	V	DVDD = 3 V. All Inputs Except MCLK IN	5
Input High Voltage (DVDD = 5 V)	VINH	2.4			V	DVDD = 5 V. All Inputs Except MCLK IN	5
Input High Voltage (DVDD = 3 V)	VINH	2			V	DVDD = 3 V. All Inputs Except MCLK IN	5
SCLK & DIN Schmitt Positive Threshold (5 V)	VT+	1.4		3	V	DVDD = 5 V NOMINAL	5
SCLK & DIN Schmitt Negative Threshold (5 V)	VT-	0.8		1.4	V	DVDD = 5 V NOMINAL	5
SCLK & DIN Schmitt Hysteresis (5 V)	VT+, VT-	0.4		0.8	V	DVDD = 5 V NOMINAL	5
SCLK & DIN Schmitt Positive Threshold (3 V)	VT+	1		2.5	V	DVDD = 3 V NOMINAL	5
SCLK & DIN Schmitt Negative Threshold (3 V)	VT-	0.4		1.1	V	DVDD = 3 V NOMINAL	5
SCLK & DIN Schmitt Hysteresis (3 V)	VT+, VT-	0.375		0.8	V	DVDD = 3 V NOMINAL	5
MCLK IN Input Low Voltage (5 V)	VINL			0.8	V	MCLK In Only, DVDD = 5 V NOMINAL	5
MCLK IN Input High Voltage (5 V)	VINH	3.5			V	MCLK In Only, DVDD = 5 V NOMINAL	5
MCLK IN Input Low Voltage (3 V)	VINL			0.4	V	MCLK In Only, DVDD = 3 V NOMINAL	5
MCLK IN Input High Voltage (3 V)	VINH	2.5			V	MCLK In Only, DVDD = 3 V NOMINAL	5
Output Low Voltage (5 V)	VOL			0.4	V	ISINK = 800 µA with DVDD = 5 V. Except for MCLK OUT	5
Output Low Voltage (3 V)	VOL			0.4	V	ISINK = 100 µA with DVDD = 3 V. Except for MCLK OUT	5
Output High Voltage (5 V)	VOH	4			V	ISOURCE = 200 µA with DVDD = 5 V. Except for MCLK OUT	5
Floating State Leakage Current		-10		10	µA		6
AVDD Current, BST=0, BUFFER = 0 V			0.22	0.28	mA	AVDD = 3 V or 5 V. BST Bit = 0, CLKDIS = 1. fCLK IN = 1 MHz or 2.4576 MHz	6
AVDD Current, BST=0, BUFFER = DVDD			0.45	0.6	mA	AVDD = 3 V or 5 V. BST Bit = 0, CLKDIS = 1. fCLK IN = 1 MHz or 2.4576 MHz	6
AVDD Current, BST=1, BUFFER = 0 V			0.38	0.5	mA	AVDD = 3 V or 5 V. BST Bit = 1. fCLK IN = 2.4576 MHz	6
AVDD Current, BST=1, BUFFER = DVDD			0.8	1.1	mA	AVDD = 3 V or 5 V. BST Bit = 1. fCLK IN = 2.4576 MHz	6
DVDD Current (3 V, 1 MHz)			0.06	0.08	mA	DVDD = 3 V. fCLK IN = 1 MHz. External MCLK IN, CLKDIS = 1	6
DVDD Current (5 V, 1 MHz)			0.13	0.16	mA	DVDD = 5 V. fCLK IN = 1 MHz. External MCLK IN, CLKDIS = 1	6
DVDD Current (3 V, 2.4576 MHz)			0.15	0.18	mA	DVDD = 3 V. fCLK IN = 2.4576 MHz. External MCLK IN, CLKDIS = 1	6
DVDD Current (5 V, 2.4576 MHz)			0.3	0.35	mA	DVDD = 5 V. fCLK IN = 2.4576 MHz. External MCLK IN, CLKDIS = 1	6
Normal-Mode Power Dissipation (3 V, BUFFER 0 V, 1 MHz)			0.84	1.05	mW	AVDD = DVDD = +3 V. BUFFER = 0 V. fCLK IN = 1 MHz. BST Bit = 0	6
Normal-Mode Power Dissipation (3 V, BUFFER +3 V, 2.4576 MHz)			1.9	2.34	mW	AVDD = DVDD = +3 V. BUFFER = +3 V. fCLK IN = 2.4576 MHz. BST Bit = 0	6
Normal-Mode Power Dissipation (5 V, BUFFER 0 V, 1 MHz)			1.75	2.1	mW	AVDD = DVDD = +5 V. BUFFER = 0 V. fCLK IN = 1 MHz. BST Bit = 0	6
Normal-Mode Power Dissipation (5 V, BUFFER +5 V, 2.4576 MHz)			3.75	4.75	mW	AVDD = DVDD = +5 V. BUFFER = +5 V. fCLK IN = 2.4576 MHz. BST Bit = 0	6
Standby (Power-Down) Current (5 V)			9	18	µA	External MCLK IN = 0 V or DVDD. VDD = +5 V	6
Standby (Power-Down) Current (3 V)			4	10	µA	External MCLK IN = 0 V or DVDD. VDD = +3 V	6
AVDD Voltage	AVDD	2.7		3.3	V	For Specified Performance (also +4.75 to +5.25 V)	6
AVDD Voltage (5 V range)	AVDD	4.75		5.25	V	For Specified Performance	6
DVDD Voltage	DVDD	2.7		5.25	V	For Specified Performance	6
Operating Temperature Range (Y Version)		-40		105	°C	Y Version	6
Master Clock Frequency	fCLKIN	0.4		2.5	MHz	Crystal/Resonator or Externally Supplied; 400 kHz min, 2.5 MHz max for specified performance	7
SYNC Pulsewidth	t1	100			ns		7
RESET Pulsewidth	t2	100			ns		7
SCLK Active Edge to Data Valid Delay (5 V)	t5	0		80	ns	DVDD = +5 V	7
SCLK Active Edge to Data Valid Delay (3 V)	t5	0		100	ns	DVDD = +3 V	7
AVDD to AGND		-0.3		7	V		8
Analog Input Voltage to AGND		-0.3			V	-0.3 V to AVDD + 0.3 V	8
Digital Input Voltage to DGND		-0.3			V	-0.3 V to DVDD + 0.3 V	8
Storage Temperature Range		-65		150	°C		8
Junction Temperature				150	°C		8
TSSOP Package Power Dissipation				450	mW	TSSOP Package	8
TSSOP Thermal Impedance	θJA		128		°C/W	TSSOP Package	8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH 2. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN PLATED	40

CAD (KiCad official)

Symbol: AD7714YRUZ-REEL7
Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
3D model: TSSOP-24 (KiCad packages3D, STEP)
3D model files: ad7714yruz-reel7-etched.step / ad7714yruz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7714yruz-reel7.step / ad7714yruz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (40 pp, sha256 a4534cb3ef873dc9, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD7714YRUZ-REEL7

Verified AD7714YRUZ-REEL7

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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