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LKS32MC035DL6S8

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LINKOSEMI Microcontroller Units (MCUs/MPUs/SOCs), SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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LKS32MC035DL6S8

LINKOSEMI · Microcontroller Units (MCUs/MPUs/SOCs) · SOP-16

LKS32MC035DL6S8 from LINKOSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Supplies the MCU at 2.5-5.5V per the recommended operating conditions and carries the 5V LDO output, with a recommended 1uF decoupling capacitor placed close to the pin.
2 P0_8 bidirectional GPIO P0.8 with CMP0_OUT, MCPWM_BKIN1, UART0_TXD, SPI_CLK, SCL, TIM0_CH0, ADC_TRIGGER, ADC_CH4 and CMP0_IP3 alternate functions, with a built-in 10kΩ pull-up that can be turned off by software.
3 P0_7 / P0_9 bidirectional Shared pin labeled P0_7 (UART0_TXD, SCL, TIM0_CH1, ADC_CH5, OPAx_OUT, EXTI5) and P0_9 (CLKO, MCPWM_CH0P, UART0_RXD, SPI_DO, SDA, ADC_CH6, CMP0_IN, EXTI7, WK3), each with a built-in 10kΩ pull-up that can be turned off by software.
4 VCC power_in Gate driver supply input rated 7.5-28V for the 035D; when VCC is above 20V, AVDD is powered from the LDO5V output, and a decoupling capacitor of at least 1uF is required between VCC and ground.
5 HO1 output Phase A high-side gate drive output, driven by MCU P0.13 with the same polarity as P0.13 (HO1 = 1 when P0.13 = 1), which requires MCPWM_SWAP = 1.
6 LO1 output Phase A low-side gate drive output, driven by MCU P0.10 with the same polarity as P0.10 (LO1 = 1 when P0.10 = 1), which requires MCPWM_SWAP = 1.
7 HO2 output Phase B high-side gate drive output, driven by MCU P0.14 per the 035D pin figure and schematic, with polarity and MCPWM_SWAP requirement not stated in the 035D table extract.
8 LO2 output Phase B low-side gate drive output, driven by MCU P0.11 per the 035D pin figure and schematic, with polarity and MCPWM_SWAP requirement not stated in the 035D table extract.
9 HO3 output Phase C high-side gate drive output, driven by MCU P0.15 per the 035D pin figure and schematic, with polarity and MCPWM_SWAP requirement not stated in the 035D table extract.
10 LO3 output Phase C low-side gate drive output, driven by MCU P0.12 per the 035D pin figure and schematic, with polarity and MCPWM_SWAP requirement not stated in the 035D table extract.
11 P1_5 bidirectional GPIO P1.5 with SPI_DI, SCL, TIM1_CH1, ADC_CH8, OPA1_IN and CMP1_IP0 alternate functions, with a built-in 10kΩ pull-up that can be turned off by software.
12 P1_3 / P1_4 / P1_7 bidirectional Shared pin labeled P1_3 (SPI_CS, TIM1_CH0, OPA1_IP), P1_4 (CMP1_OUT, MCPWM_BKIN0, SPI_CS, TIM0_CH1, CMP1_IN, PU) and P1_7 (CMP0_OUT, HALL_IN0, MCPWM_CH2P, UART0_RXD, TIM0_CH0, ADC_TRIGGER, CMP1_IP1, PU).
13 P1_8 bidirectional GPIO P1.8 with SWCLK, HALL_IN2, MCPWM_CH3P, UART0_TXD, SCL, TIM1_CH0, ADC_TRIGGER and CMP1_IP3 alternate functions, with a built-in 10kΩ pull-up that can be turned off by software.
14 P1_9 bidirectional GPIO P1.9 with SWDAT, MCPWM_CH3N, UART0_RXD, SDA, TIM1_CH1 and ADC_CH9 alternate functions, with a built-in 10kΩ pull-up that can be turned off by software.
15 P0_0 / P0_2 / P0_3 bidirectional Shared pin labeled P0_0 (MCPWM_BKIN0, UART0_RXD, ADC_CH10, REF, LDO15, DAC_OUT), P0_2 (SPI_DI, RST_n, used as RSTN by default with a 10nF-100nF capacitor to ground) and P0_3 (TIM1_CH0, OPA0_IN_B).
16 GND power_in Ground pin, which should be grounded uniformly with the other ground pins on the PCB.

Key specifications

Parameter Value
Manufacturer LINKOSEMI
Package SOP-16
Category Single Chip Microcomputer/Microcontroller
Pins 16

CAD (KiCad official)

  • Symbol: LKS32MC035DL6S8
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: lks32mc035dl6s8-etched.step / lks32mc035dl6s8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lks32mc035dl6s8.step / lks32mc035dl6s8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LINKOSEMI datasheet (118 pp, sha256 1c32edb1f3151627, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF