component
TPS71718QDRVRQ1
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS71718QDRVRQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)
TPS71718QDRVRQ1 from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | This pin is the regulated output voltage, and a minimum capacitance of 1 μF is required for stability from this pin to ground. |
| 2 | NR | passive | Fixed-voltage versions only; an external capacitor connected to this pin bypasses noise generated by the internal band gap, thus lowering output noise. |
| 3 | GND | power_in | Ground reference pin, which should be connected with wide copper return paths to the input and output capacitors as close to the pin as possible. |
| 4 | EN | input | Driving the enable pin above VEN(high) turns on the regulator, and driving it below VEN(low) puts the regulator into standby mode, disabling the output and reducing operating current. |
| 5 | N/C | unconnected | Not connected; this pin can be tied to ground to improve thermal dissipation. |
| 6 | IN | input | Input to the device, where a 0.1-μF to 1-μF capacitor is recommended for better performance. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.5 | 6.5 | V | 7 | ||
| Output voltage | VOUT | 0.9 | 5 | V | TPS717-Q1 | 6 | |
| Output current | IOUT | 0 | 150 | mA | 6 | ||
| Output capacitor | COUT | 1 | 100 | µF | 6 | ||
| Junction temperature | TJ | -40 | 125 | °C | 6 | ||
| Input voltage | VIN | -0.3 | 7 | V | all voltages with respect to GND | 5 | |
| Output voltage | VOUT | -0.3 | 7 | V | all voltages with respect to GND | 5 | |
| Noise reduction pin voltage | VNR | -0.3 | 3.6 | V | all voltages with respect to GND | 5 | |
| Ambient temperature | TA | -40 | 125 | °C | 5 | ||
| Operating junction temperature | TJ | -55 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 5 | ||
| Output accuracy (VOUT ≥ 1 V) | -3 | 3 | % | Over VIN, IOUT, temperature; VOUT + 0.5 V ≤ VIN ≤ 6.5 V, 0 mA ≤ IOUT ≤ 150 mA | 7 | ||
| Dropout voltage | VDO | 170 | 300 | mV | VIN = VOUT(nom), 0.1 V, IOUT = 150 mA | 7 | |
| Output current limit (fixed output) | ILIM (fixed) | 200 | 325 | 575 | mA | VOUT = 0.9 × VOUT(nom) | 7 |
| Ground pin current | IGND | 45 | 80 | µA | IOUT = 0.1 mA | 7 | |
| Ground pin current | IGND | 100 | µA | IOUT = 150 mA | 7 | ||
| Shutdown current (IGND) | ISHDN | 0.2 | 1.5 | µA | VEN ≤ 0.4 V, 2.5 V ≤ VIN < 4.5 V, TA = -40°C to 125°C | 7 | |
| Shutdown current (IGND) | ISHDN | 0.9 | µA | VEN ≤ 0.4 V, 4.5 V ≤ VIN ≤ 6.5 V, TA = -40°C to 125°C | 7 | ||
| Shutdown current (IGND), DRV package | ISHDN | 2 | µA | VEN ≤ 0.4 V, 2.5 V ≤ VIN < 4.5 V, TA = -40°C to 125°C, DRV package | 7 | ||
| Enable high (enabled) | VEN(high) | 1.2 | 6.5 | V | VIN ≤ 5.5 V | 7 | |
| Enable high (enabled) | VEN(high) | 1.25 | 6.5 | V | 5.5 V < VIN ≤ 6.5 V | 7 | |
| Enable low (shutdown) | VEN(low) | 0 | 0.4 | V | 7 | ||
| Enable pin current, enabled | IEN(high) | 0.02 | 1 | µA | EN = 6.5 V | 7 | |
| Junction-to-ambient thermal resistance (DRV) | RθJA | 71.1 | °C/W | DRV (WSON) 6 pins | 6 | ||
| Junction-to-case (top) thermal resistance (DRV) | RθJC(top) | 96.5 | °C/W | DRV (WSON) 6 pins | 6 | ||
| Junction-to-board thermal resistance (DRV) | RθJB | 40.5 | °C/W | DRV (WSON) 6 pins | 6 | ||
| Junction-to-top characterization parameter (DRV) | ψJT | 2.7 | °C/W | DRV (WSON) 6 pins | 6 | ||
| Junction-to-board characterization parameter (DRV) | ψJB | 40.9 | °C/W | DRV (WSON) 6 pins | 6 | ||
| Junction-to-case (bottom) thermal resistance (DRV) | RθJC(bot) | 10.7 | °C/W | DRV (WSON) 6 pins | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitor, and to the LDO ground pin as close to the GND pin as possible, connected by wide, component-side, copper surface area. The use of vias and long traces to create LDO component connections is | 21 |
CAD (KiCad official)
- Symbol:
TPS71718QDRVRQ1 - Footprint:
Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm - 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
tps71718qdrvrq1-etched.step/tps71718qdrvrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps71718qdrvrq1.step/tps71718qdrvrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
2be05880cde1a822, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).