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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

AD9288BSTZ-100

Analog Devices · Analog To Digital Converters (ADCs) · LQFP-48(7x7)

AD9288BSTZ-100 from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground.
2	AINA	input	Analog input for Channel A; 1 V p-p differential range, 0.3×VD ±0.2 V common-mode.
3	AINA	input	Complementary analog input for Channel A; differential pair with Pin 2.
4	DFS	input	Data format select; low for offset binary output, high for twos complement output.
5	REFINA	power_in	Reference voltage input for Channel A; 1.2 V to 1.3 V external reference or connect to REFOUT.
6	REFOUT	power_out	Internal 1.25 V reference voltage output; can supply external reference or serve as feedback.
7	REFINB	power_in	Reference voltage input for Channel B; 1.2 V to 1.3 V external reference or connect to REFOUT.
8	S1	input	User select 1; tied to VD; with S2 controls standby mode and data alignment mode per Table 4.
9	S2	input	User select 2; tied to VD; with S1 controls standby mode and data alignment mode per Table 4.
10	AINB	input	Complementary analog input for Channel B; differential pair with Pin 11.
11	AINB	input	Analog input for Channel B; 1 V p-p differential range, 0.3×VD ±0.2 V common-mode.
12	GND	power_in	Ground.
13	VD	power_in	Analog supply; 3.0 V nominal (2.7 V to 3.6 V operating range).
14	ENCB	input	Encode clock input for Channel B; TTL/CMOS compatible, sources pipeline ADC for independent channel operation.
15	VDD	power_in	Digital supply; 3.0 V nominal (2.5 V to 3.6 V operating range) for output drivers.
16	GND	power_in	Ground.
17	D7B	output	Digital output for Channel B, bit 7 (MSB); TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
18	D6B	output	Digital output for Channel B, bit 6; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
19	D5B	output	Digital output for Channel B, bit 5; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
20	D4B	output	Digital output for Channel B, bit 4; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
21	D3B	output	Digital output for Channel B, bit 3; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
22	D2B	output	Digital output for Channel B, bit 2; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
23	D1B	output	Digital output for Channel B, bit 1; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
24	D0B	output	Digital output for Channel B, bit 0 (LSB); TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
25	NC	unconnected	No connect; leave unconnected.
26	NC	unconnected	No connect; leave unconnected.
27	GND	power_in	Ground.
28	VDD	power_in	Digital supply; 3.0 V nominal (2.5 V to 3.6 V operating range) for output drivers.
29	GND	power_in	Ground.
30	VD	power_in	Analog supply; 3.0 V nominal (2.7 V to 3.6 V operating range).
31	VD	power_in	Analog supply; 3.0 V nominal (2.7 V to 3.6 V operating range).
32	GND	power_in	Ground.
33	VDD	power_in	Digital supply; 3.0 V nominal (2.5 V to 3.6 V operating range) for output drivers.
34	GND	power_in	Ground.
35	NC	unconnected	No connect; leave unconnected.
36	NC	unconnected	No connect; leave unconnected.
37	D0A	output	Digital output for Channel A, bit 0 (LSB); TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
38	D1A	output	Digital output for Channel A, bit 1; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
39	D2A	output	Digital output for Channel A, bit 2; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
40	D3A	output	Digital output for Channel A, bit 3; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
41	D4A	output	Digital output for Channel A, bit 4; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
42	D5A	output	Digital output for Channel A, bit 5; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
43	D6A	output	Digital output for Channel A, bit 6; TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
44	D7A	output	Digital output for Channel A, bit 7 (MSB); TTL/CMOS compatible, 4.5 ns to 6.0 ns propagation delay.
45	GND	power_in	Ground.
46	VDD	power_in	Digital supply; 3.0 V nominal (2.5 V to 3.6 V operating range) for output drivers.
47	ENCA	input	Encode clock input for Channel A; TTL/CMOS compatible, sources pipeline ADC for independent channel operation.
48	VD	power_in	Analog supply; 3.0 V nominal (2.7 V to 3.6 V operating range).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-48(7x7)
Category	ADC/DAC/Data Conversion
Pins	48

CAD (KiCad official)

Symbol: AD9288BSTZ-100
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: ad9288bstz-100-etched.step / ad9288bstz-100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9288bstz-100.step / ad9288bstz-100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 881f700c9df1b8fd, retrieved 2026-09-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF