LTM4632EY#PBF from Analog Devices, in a BGA-25. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
A1	VOUT2	power_out	Power output pin of the Channel 2 switching regulator; apply the load between this pin and GND, with output decoupling placed directly at the pins.
A2	VIN	power_in	Power input pin; apply the 3.6V to 15V input between the VIN and GND pins with input decoupling placed directly between them.
A3	VTTR	power_out	Low-noise reference output equal to VDDQIN/2 that can supply 10mA for DDR memory, with an internal 0.01µF capacitor.
A4	VDDQIN	input	External reference input for Channel 2; an internal resistor divider sets the VTTR pin to half the voltage applied to this input.
A5	COMP2	passive	Current control threshold and error amplifier compensation point of Channel 2, with a normal range of 0.3V to 1.8V.
B1	VOUT2	power_out	Power output pin of the Channel 2 switching regulator; apply the load between this pin and GND, with output decoupling placed directly at the pins.
B2	RUN2	input	Run control input for Channel 2; tie above 1.28V to enable the channel, tie below 1V to shut it down, and do not float this pin.
B3	VIN	power_in	Power input pin; apply the 3.6V to 15V input between the VIN and GND pins with input decoupling placed directly between them.
B4	PGOOD2	output	Open-drain power good output pulled low when VOUT2 is outside ±8% (typical) of VDDQIN/2, with 15mV of hysteresis.
B5	GND	power_in	Power ground pin for both the input and output returns.
C1	GND	power_in	Power ground pin for both the input and output returns.
C2	GND	power_in	Power ground pin for both the input and output returns.
C3	INTVCC	power_out	Internal 3.3V regulator output that powers the internal drivers and control circuits, internally decoupled to GND with a 2.2µF ceramic capacitor.
C4	SGND	power_in	Ground pin printed as SGND in the pinout table and as a power ground in the Pin Functions section, to be used as a ground return.
C5	SYNC/MODE	input	Mode select and external synchronization input; tie to GND for forced continuous operation, float or tie to INTVCC for Burst Mode at light load, or drive with a clock to synchronize the switching frequency.
D1	VOUT1	power_out	Power output pin of the Channel 1 switching regulator; apply the load between this pin and GND, with output decoupling placed directly at the pins.
D2	RUN1	input	Run control input for Channel 1; tie above 1.28V to enable the channel, tie below 1V to shut it down, and do not float this pin.
D3	VIN	power_in	Power input pin; apply the 3.6V to 15V input between the VIN and GND pins with input decoupling placed directly between them.
D4	PGOOD1	output	Open-drain power good output pulled low when FB1 is outside ±8% (typical) of the internal 0.6V reference, with 15mV of hysteresis.
D5	GND	power_in	Power ground pin for both the input and output returns.
E1	VOUT1	power_out	Power output pin of the Channel 1 switching regulator; apply the load between this pin and GND, with output decoupling placed directly at the pins.
E2	VIN	power_in	Power input pin; apply the 3.6V to 15V input between the VIN and GND pins with input decoupling placed directly between them.
E3	TRACK/SS1	input	Output tracking and soft-start pin for Channel 1; a voltage below 0.6V servos FB1 to this pin, and the internal 1.2µA pull-up from INTVCC lets a capacitor set the soft-start.
E4	FB1	input	Negative input of the Channel 1 error amplifier, internally connected to VOUT1 through a 60.4k resistor, with an external resistor to GND programming the output voltage.
E5	COMP1	passive	Current control threshold and error amplifier compensation point of Channel 1, with a normal range of 0.3V to 1.8V.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	BGA-25
Category	Power Management ICs
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input DC Voltage	VIN	3.6		15	V		3
3.3V Input DC Voltage	VIN_3.3	3.1	3.3	3.5	V	VIN = INTVCC	3
Output Voltage Range (CH1)	VOUT1(RANGE)	0.6		2.5	V	VIN = 3.6V to 15V	3
Output Voltage Range (CH2)	VOUT2(RANGE)			1.8	V	VIN = 3.6V to 15V	3
CH1 Output Voltage, Total Variation with Line and Load	VOUT1(DC)	1.28	1.3	1.32	V	CIN = 22µF, COUT = 100µF Ceramic, RFB1 = 51.7k, MODE = GND, IOUT = -3A to 3A	3
CH1 Output Continuous Current Range	IOUT1(DC)	-3		3	A	VIN = 12V, VOUT1 = 1.3V (Note 3)	3
CH1 Input Supply Bias Current	IQ1(VIN)			13	mA	VIN = 12V, VOUT1 = 1.3V, MODE = GND	3
CH1 Input Supply Bias Current	IQ1(VIN)			400	µA	VIN = 12V, VOUT1 = 1.3V, MODE = INTVCC	3
CH1 Input Supply Bias Current (shutdown)	IQ1(VIN)			40	µA	Shutdown, RUN1 = GND	3
CH1 Input Supply Current	IS1(VIN)			0.4	A	VIN = 12V, VOUT1 = 1.3V, IOUT = 3A	3
CH1 Line Regulation Accuracy	ΔVOUT1(Line)/VOUT1		0.01	0.05	%/V	VOUT1 = 1.3V, VIN = 3.6V to 15V, IOUT1 = 0A	3
CH1 Load Regulation Accuracy	ΔVOUT1(Load)/VOUT1		0.2	1	%	VOUT1 = 1.3V, IOUT = -3A to 3A	3
CH1 Output Ripple Voltage	VOUT1(AC)			30	mV	IOUT = 0A, COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V	3
CH1 Turn-On Overshoot	ΔVOUT1(START)			30	mV	IOUT = 0A, COUT = 47µF Ceramic, TRACK/SS1 = -0.1µF, VIN = 12V, VOUT1 = 1.3V	3
Turn-On Time	tSTART			5.5	ms	COUT = 100µF Ceramic, TRACK/SS1 = 0.01µF, No Load, VIN = 12V, VOUT1 = 1.3V	3
CH1 Peak Deviation for Dynamic Load	ΔVOUTLS1			85	mV	Load: 0% to 25% to 0% of Full Load, COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V	3
CH1 Settling Time for Dynamic Load Step	tSETTLE1			20	µs	Load: 0% to 25% to 0% of Full Load, COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V	3
CH1 Output Current Limit	IOUTPK1			4.5	A	VIN = 12V, VOUT1 = 1.3V	3
CH2 Output Voltage, Total Variation with Line and Load	VOUT2(DC)	637	650	663	mV	CIN = 22µF, COUT = 100µF Ceramic, VDDQIN= 1.3V, MODE = GND, IOUT = -3A to 3A	3
CH2 Output Continuous Current Range	IOUT2(DC)	-3		3	A	VIN = 12V, VDDQIN = 1.3V (Note 3)	3
CH2 Input Supply Bias Current	IQ2(VIN)			7	mA	VIN = 12V, VDDQIN = 1.3V, MODE = GND	3
CH2 Input Supply Bias Current (shutdown)	IQ2(VIN)			40	µA	Shutdown, RUN2 = 0	3
CH2 Input Supply Current	IS2(VIN)			0.25	A	VIN = 12V, VDDQIN = 1.3V, IOUT = 3A	3
CH2 Line Regulation Accuracy	ΔVOUT2(Line)/VOUT2		0.01	0.05	%/V	VDDQIN = 1.3V, VIN = 3.6V to 15V, IOUT2 = 0A	3
CH2 Load Regulation Accuracy	ΔVOUT2(Load)/VOUT2		0.2	1	%	VDDQIN = 1.3V, IOUT = -3A to 3A	3
CH2 Output Ripple Voltage	VOUT2(AC)			30	mV	IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V, VDDQIN = 1.3V	3
CH2 Peak Deviation for Dynamic Load	ΔVOUTLS2			85	mV	Load: 0% to 25% to 0% of Full Load, COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V	3
CH2 Settling Time for Dynamic Load Step	tSETTLE2			20	µs	Load: 0% to 25% to 0% of Full Load, COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V	3
CH2 Output Current Limit	IOUTPK2			4.5	A		3
Voltage at VFB1 Pin	VFB1	0.593	0.6	0.607	V	IOUT = 0A, VOUT1 = 1.3V	4
Current at VFB1 Pin	IFB1	-30		30	nA	(Note 4)	4
Resistor Between VOUT1 and VFB1 Pins	RFBHI1	60	60.4	60.8	kΩ		4
VTTR Voltage Reference (values are multiples of VDDQIN)	VTTR	0.492	0.5	0.508	V	VDDQIN = 1.3V, IVTTR = ±10mA, CVTTR < 10nF; min/typ/max printed as x VDDQIN	4
RUN Pin On Threshold (rising)	VRUN1, VRUN2	1.18	1.28	1.39	V	RUN Threshold Rising	4
RUN Pin On Threshold (falling)	VRUN1, VRUN2	0.95	1.01	1.05	V	RUN Threshold Falling	4
RUN Pin Leakage Current	IRUN1, IRUN2	-1	0	1	µA		4
Minimum On-Time	tON(MIN)			20	ns	(Note 4)	4
Minimum Off-Time	tOFF(MIN)			45	ns	(Note 4)	4
PGOOD Trip Level, VFB with respect to 0.6V	VPGOOD	-8		8	%	Ramping Negative / Ramping Positive	4
PGOOD Trip Level, VOUT2 with respect to VDDQIN/2	VPGOOD	-14		14	%	Ramping Negative / Ramping Positive (Note 4)	4
PGOOD Pull-Down Resistance	RPGOOD			15	Ω	1mA Load	4
Internal VCC Voltage	VINTVCC	3.1	3.3	3.5	V	VIN = 3.6V to 15V	4
INTVCC Load Regulation	VINTVCC Load Reg			1.3	%	ICC = 0 to 50mA	4
Oscillator Frequency	fOSC			1	MHz		4
SYNC Threshold Voltage	SYNC			0.95	V		4
MODE Input Current	ISYNC/MODE			-1.5	µA	SYNC/MODE = INTVCC	4
Absolute Max VIN	VIN	-0.3		16	V		2
Absolute Max VOUT	VOUT	-0.3		6	V		2
Absolute Max PGOOD1, PGOOD2	PGOOD1, PGOOD2	-0.3		16	V		2
Absolute Max RUN1, RUN2	RUN1, RUN2	-0.3			V	max = VIN+0.3V as printed	2
Absolute Max INTVCC, TRACK/SS1, VDDQIN, VTTR	INTVCC, TRACK/SS1, VDDQIN, VTTR	-0.3		3.6	V		2
Absolute Max SYNC/MODE, COMP1, COMP2, FB1, FB2	SYNC/MODE, COMP1, COMP2, FB1, FB2	-0.3			V	max = INTVCC as printed	2
Operating Internal Temperature Range	TJ	-40		125	°C	Notes 2, 3, 5	2
Storage Temperature Range	TSTG	-55		125	°C		2
Maximum Junction Temperature	TJMAX			125	°C		2
Junction-to-Case (top) Thermal Resistance	θJCtop		17		°C/W		2
Junction-to-Case (bottom) Thermal Resistance	θJCbottom		11		°C/W		2
Junction-to-Board plus Board-to-Ambient Thermal Resistance	θJB +θBA		22		°C/W		2
Junction-to-Ambient Thermal Resistance	θJA		20		°C/W	JESD 51-9 test board	2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND	21

CAD (KiCad official)

Symbol: LTM4632EY#PBF
Footprint: Package_BGA:BGA-25_6.35x6.35mm_Layout5x5_P1.27mm
3D model: BGA-25 (KiCad packages3D, STEP)
3D model files: ltm4632ey-pbf-etched.step / ltm4632ey-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltm4632ey-pbf.step / ltm4632ey-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 641fe753b308fd12, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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