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SN74ACT240DWR

Public Made by Adom

by adom

Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74ACT240DWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20

SN74ACT240DWR from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable 1 (active low): when low, the 1Y outputs pass the inverted 1A data; when high, the 1Y outputs are high-impedance.
2 1A1 input Data input 1A1 of buffer section 1; unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V.
3 2Y4 output Balanced CMOS push-pull output 2Y4 (inverting buffer, section 2); recommended IOH −24 mA and IOL 24 mA, and unused outputs must be left open.
4 1A2 input Data input 1A2 of buffer section 1; unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V.
5 2Y3 output Balanced CMOS push-pull output 2Y3 (inverting buffer, section 2); recommended IOH −24 mA and IOL 24 mA, and unused outputs must be left open.
6 1A3 input Data input 1A3 of buffer section 1; unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V.
7 2Y2 output Balanced CMOS push-pull output 2Y2 (inverting buffer, section 2); recommended IOH −24 mA and IOL 24 mA, and unused outputs must be left open.
8 1A4 input Data input 1A4 of buffer section 1; unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V.
9 2Y1 output Balanced CMOS push-pull output 2Y1 (inverting buffer, section 2); recommended IOH −24 mA and IOL 24 mA, and unused outputs must be left open.
10 GND power_in Ground pin; unused inputs must be tied to VCC or GND.
11 2A1 input Data input 2A1 of buffer section 2; unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V.
12 1Y4 output Balanced CMOS push-pull output 1Y4 (inverting buffer, section 1); recommended IOH −24 mA and IOL 24 mA, and unused outputs must be left open.
13 2A2 input Data input 2A2 of buffer section 2; unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V.
14 1Y3 output Balanced CMOS push-pull output 1Y3 (inverting buffer, section 1); recommended IOH −24 mA and IOL 24 mA, and unused outputs must be left open.
15 2A3 input Data input 2A3 of buffer section 2; unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V.
16 1Y2 output Balanced CMOS push-pull output 1Y2 (inverting buffer, section 1); recommended IOH −24 mA and IOL 24 mA, and unused outputs must be left open.
17 2A4 input Data input 2A4 of buffer section 2; unused inputs must be held at VCC or GND, with VIH minimum 2 V and VIL maximum 0.8 V.
18 1Y1 output Balanced CMOS push-pull output 1Y1 (inverting buffer, section 1); recommended IOH −24 mA and IOL 24 mA, and unused outputs must be left open.
19 2OE input Output enable 2 (active low): when low, the 2Y outputs pass the inverted 2A data; when high, the 2Y outputs are high-impedance.
20 VCC power_in Supply voltage, 4.5 V to 5.5 V; a pull-up from OE to VCC is recommended to hold outputs high-impedance during power-up or power-down.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74ACT240DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20 (KiCad packages3D, STEP)
  • 3D model files: sn74act240dwr-etched.step / sn74act240dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74act240dwr.step / sn74act240dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 bfe8f6899871a470, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF