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DM9000EP

Public Made by Adom

by adom

DAVICOM Ethernet Controllers, LQFP-100(14x14). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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DM9000EP

DAVICOM · Ethernet Controllers · LQFP-100(14x14)

DM9000EP from DAVICOM, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IOR# input Processor Read Command, low active at default, polarity modifiable via EEPROM.
2 IOW# input Processor Write Command, low active at default, polarity modifiable via EEPROM.
3 AEN input Address Enable, low active signal used to select the DM9000.
4 IOWAIT output Processor Command Ready, pulled low when command issued before last command completed.
5 DVDD power_in Digital power supply (3.3V).
6 SD0 bidirectional Processor Data Bus bit 0, supports 8/16/32-bit data width modes.
7 SD1 bidirectional Processor Data Bus bit 1, supports 8/16/32-bit data width modes.
8 SD2 bidirectional Processor Data Bus bit 2, supports 8/16/32-bit data width modes.
9 SD3 bidirectional Processor Data Bus bit 3, supports 8/16/32-bit data width modes.
10 SD4 bidirectional Processor Data Bus bit 4, supports 8/16/32-bit data width modes.
11 SD5 bidirectional Processor Data Bus bit 5, supports 8/16/32-bit data width modes.
12 SD6 bidirectional Processor Data Bus bit 6, supports 8/16/32-bit data width modes.
13 SD7 bidirectional Processor Data Bus bit 7, supports 8/16/32-bit data width modes.
14 RST input Hardware Reset Command, active high to reset the DM9000, device ready 5us after deassert.
15 DGND power_in Digital ground.
16 TEST1 input Operation Mode test bit 1, set to (1,1,0,0) for normal application.
17 TEST2 input Operation Mode test bit 2, set to (1,1,0,0) for normal application.
18 TEST3 input Operation Mode test bit 3, set to (1,1,0,0) for normal application.
19 TEST4 input Operation Mode test bit 4, set to (1,1,0,0) for normal application.
20 DGND power_in Digital ground.
21 X2_25M output Crystal 25MHz oscillator output for external crystal or oscillator connection.
22 X1_25M input Crystal 25MHz oscillator input for external crystal or oscillator connection.
23 DGND power_in Digital ground.
24 NC unconnected No Connect.
25 BGGND power_in Bandgap ground.
26 BGRES bidirectional Bandgap resistor pin, use 6.8kΩ 1% resistor to ground for normal operation.
27 AVDD power_in Bandgap and Guard Ring power supply (3.3V).
28 AVDD power_in RX analog power supply (3.3V).
29 RXI+ input Twisted pair RX input positive for 10/100Base-T reception.
30 RXI- input Twisted pair RX input negative for 10/100Base-T reception.
31 AGND power_in RX analog ground.
32 AGND power_in TX analog ground.
33 TXO+ output Twisted pair TX output positive for 10/100Base-T transmission.
34 TXO- output Twisted pair TX output negative for 10/100Base-T transmission.
35 AVDD power_in TX analog power supply (3.3V).
36 DVDD power_in Digital power supply (3.3V).
37 LINK_I input External MII device link status input for reverse MII interface.
38 RXD3 input External MII Receive Data bit 3, 4-bit nibble synchronous to RXCLK in 10/100 Mbps mode.
39 RXD2 input External MII Receive Data bit 2, 4-bit nibble synchronous to RXCLK in 10/100 Mbps mode.
40 RXD1 input External MII Receive Data bit 1, 4-bit nibble synchronous to RXCLK in 10/100 Mbps mode.
41 RXD0 input External MII Receive Data bit 0, 4-bit nibble synchronous to RXCLK in 10/100 Mbps mode.
42 DGND power_in Digital ground.
43 CRS bidirectional External MII Carrier Sense, active high for carrier presence, output in reverse MII mode.
44 COL bidirectional External MII Collision Detect, active high for collision indication, output in reverse MII mode.
45 RX_DV input External MII Receive Data Valid, indicates valid data present on RXD during frame reception.
46 RX_ER input External MII Receive Error, indicates error detected during frame reception.
47 RX_CLK input External MII Receive Clock for synchronizing received data in 10/100 Mbps modes.
48 TEST5 input Test pin, must be connected to ground for normal operation.
49 TX_CLK bidirectional External MII Transmit Clock, input in reverse MII, output in normal MII mode.
50 TXD0 output External MII Transmit Data bit 0, 4-bit nibble synchronous to TX_CLK in 10/100 Mbps mode.
51 TXD1 output External MII Transmit Data bit 1, 4-bit nibble synchronous to TX_CLK in 10/100 Mbps mode.
52 TXD2 output External MII Transmit Data bit 2, also used as IO base address strap pin.
53 TXD3 output External MII Transmit Data bit 3, also used as IO base address strap pin.
54 TX_EN output External MII Transmit Enable, indicates valid data on TXD during frame transmission.
55 DVDD power_in Digital power supply (3.3V).
56 MDIO bidirectional MII Serial Management Data, bidirectional open-drain for PHY/EEPROM access.
57 MDC output MII Serial Management Clock, also used as INT pin polarity strap (high=low active).
58 DGND power_in Digital ground.
59 CLK20MO output 20MHz clock output for external MII device clock signal.
60 SPEED100# output Speed LED indicator, low active output for 100M speed, floating for 10M mode.
61 DUP# output Full-duplex LED indicator, output function depends on LED mode selection.
62 LINKACT# output Link Activity LED indicator, low active output for link/carrier status.
63 DGND power_in Digital ground.
64 EEDI input EEPROM data input for serial data reception during EEPROM operations.
65 EEDO bidirectional EEPROM data output/strap pin for serial data and data width configuration.
66 EECK output EEPROM clock output for serial EEPROM communication.
67 EECS bidirectional EEPROM chip select/strap pin for LED mode configuration.
68 GPIO0 bidirectional General Purpose I/O port 0, output mode default high to power down internal PHY.
69 GPIO1 bidirectional General Purpose I/O port 1, programmable input/output via GPCR and GPR registers.
70 GPIO2 bidirectional General Purpose I/O port 2, programmable input/output via GPCR and GPR registers.
71 GPIO3 bidirectional General Purpose I/O port 3, programmable input/output via GPCR and GPR registers.
72 DVDD power_in Digital power supply (3.3V).
73 DVDD power_in Digital power supply (3.3V).
74 NC unconnected No Connect.
75 NC unconnected No Connect.
76 DGND power_in Digital ground.
77 NC unconnected No Connect.
78 LINK_O output Cable Link Status output active high, also strap pin for reverse MII mode selection.
79 WAKEUP output Wake-up signal output on wake-up event occurrence.
80 PW_RST# input Power-on Reset input, active low to initialize DM9000, device ready 5us after deassertion.
81 DGND power_in Digital ground.
82 SD15 bidirectional Processor Data Bus bit 15, supports 8/16/32-bit data width modes.
83 SD14 bidirectional Processor Data Bus bit 14, supports 8/16/32-bit data width modes.
84 SD13 bidirectional Processor Data Bus bit 13, supports 8/16/32-bit data width modes.
85 SD12 bidirectional Processor Data Bus bit 12, supports 8/16/32-bit data width modes.
86 SD11 bidirectional Processor Data Bus bit 11, supports 8/16/32-bit data width modes.
87 SD10 bidirectional Processor Data Bus bit 10, supports 8/16/32-bit data width modes.
88 SD9 bidirectional Processor Data Bus bit 9, supports 8/16/32-bit data width modes, no internal pull-down resistor.
89 SD8 bidirectional Processor Data Bus bit 8, supports 8/16/32-bit data width modes, no internal pull-down resistor.
90 DVDD power_in Digital power supply (3.3V).
91 IO16 output Word Command indication, low active output asserted for 16-bit or 32-bit data access.
92 CMD input Command type selection, high for DATA port access, low for ADDRESS port access.
93 SA4 input Address Bus bit 4, used with SA5-9 and AEN to select DM9000.
94 SA5 input Address Bus bit 5, used with SA4,6-9 and AEN to select DM9000.
95 SA6 input Address Bus bit 6, used with SA4-5,7-9 and AEN to select DM9000.
96 SA7 input Address Bus bit 7, must be low for DM9000 selection.
97 SA8 input Address Bus bit 8, must be high for DM9000 selection.
98 SA9 input Address Bus bit 9, must be high for DM9000 selection.
99 DGND power_in Digital ground.
100 INT output Interrupt request output, high active at default, polarity modifiable via EEPROM or MDC strap pin.

Key specifications

Parameter Value
Manufacturer DAVICOM
Package LQFP-100(14x14)
Category Interface
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage DVDD AVDD -0.3 3.6 V 37
DC Input Voltage VIN -0.5 5.5 V 37
DC Output Voltage VOUT -0.3 3.6 V 37
Storage Temperature Range Tstg -65 150 °C EIAJ-4701 37
Ambient Temperature TA 0 70 ℃ 37
Lead Temp. (TL, Soldering, 10 sec.) LT 235 °C Pb-Free 37
ESD rating ESD 3000 V Rzap=1.5k Czap=100PF, Human Body Model 37
Supply Voltage (operating) DVDD,AVDD 3.135 3.465 V 37
100BASE-TX power dissipation current PD 100 mA 3.3V, 100BASE-TX 37
10BASE-T TX power dissipation current PD 85 mA 3.3V, 10BASE-T TX 37
10BASE-T idle power dissipation current PD 44 mA 3.3V, 10BASE-T idle 37
Auto-negotiation power dissipation current PD 60 mA 3.3V, Auto-negotiation 37
Power Reduced Mode power dissipation current (without cable) PD 20 mA 3.3V, Power Reduced Mode (without cable) 37
Power Down Mode power dissipation current PD 10 mA 3.3V, Power Down Mode 37
Input Low Voltage VIL 0.8 V 38
Input High Voltage VIH 2 V 38
Input Low Leakage Current IIL -1 uA VIN = 0.0V 38
Input High Leakage Current IIH 1 uA VIN = 3.3V 38
Output Low Voltage VOL 0.4 V IOL = 4mA 38
Output High Voltage VOH 2.4 V IOH = -4mA 38
100TX+/- Differential Output Voltage VTD100 1.9 2 2.1 V Peak to Peak 38
10TX+/- Differential Output Voltage VTD10 4.4 5 5.6 V Peak to Peak 38
100TX+/- Differential Output Current ITD100 19 20 21 mA Absolute Value 38
10TX+/- Differential Output Current ITD10 44 50 56 mA Absolute Value 38
100TX+/- Differential Rise/Fall Time tTR/F 3 5 ns 39
100TX+/- Differential Rise/Fall Time Mismatch tTM 0 0.5 ns 39
100TX+/- Differential Output Duty Cycle Distortion tTDC 0 0.5 ns 39
100TX+/- Differential Output Peak-to-Peak Jitter tT/T 0 1.4 ns 39
100TX+/- Differential Voltage Overshoot XOST 0 5 % 39
Oscillator period (TCKC) tCKC 39.998 40 40.002 ns 50ppm 39
OSC Pulse Width High tPWH 16 20 24 ns 39
OSC Pulse Width Low tPWL 16 20 24 ns 39

CAD (KiCad official)

  • Symbol: DM9000EP
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: dm9000ep-etched.step / dm9000ep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dm9000ep.step / dm9000ep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: DAVICOM datasheet (53 pp, sha256 9d8c421b59b355e3, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF