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SQ4937EY-T1_GE3

Public Made by Adom

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Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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SQ4937EY-T1_GE3

Vishay Intertech · MOSFETs · SO-8

SQ4937EY-T1_GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of P-channel MOSFET 1 in the dual-P-channel device; the device ratings are VDS -30 V and VGS ±20 V.
2 G1 input Gate of P-channel MOSFET 1; the absolute maximum gate-source voltage is ±20 V.
3 S2 passive Source of P-channel MOSFET 2 in the dual-P-channel device; the device ratings are VDS -30 V and VGS ±20 V.
4 G2 input Gate of P-channel MOSFET 2; the absolute maximum gate-source voltage is ±20 V.
5 D2 passive Drain of P-channel MOSFET 2 (internally tied to pin 6); the drain-source voltage limit is -30 V and continuous drain current per leg is -5 A at TC = 25 °C.
6 D2 passive Drain of P-channel MOSFET 2 (internally tied to pin 5); the drain-source voltage limit is -30 V and continuous drain current per leg is -5 A at TC = 25 °C.
7 D1 passive Drain of P-channel MOSFET 1 (internally tied to pin 8); the drain-source voltage limit is -30 V and continuous drain current per leg is -5 A at TC = 25 °C.
8 D1 passive Drain of P-channel MOSFET 1 (internally tied to pin 7); the drain-source voltage limit is -30 V and continuous drain current per leg is -5 A at TC = 25 °C.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS -30 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID -5 A TC = 25 °C 1
Continuous Drain Current ID -3 A TC = 125 °C 1
Continuous Source Current (Diode Conduction) IS -3 A 1
Pulsed Drain Current IDM -20 A Pulse test; pulse width 300 μs, duty cycle 2 % 1
Single Pulse Avalanche Current IAS -10 A L = 0.1 mH 1
Single Pulse Avalanche Energy EAS 5 mJ 1
Maximum Power Dissipation PD 3.3 W TC = 25 °C 1
Maximum Power Dissipation PD 1.1 W TC = 125 °C 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 175 °C 1
Junction-to-Ambient RthJA 110 °C/W PCB mount (note b: 1 in square PCB, FR-4) 1
Junction-to-Foot (Drain) RthJF 45 °C/W 1
Drain-Source Breakdown Voltage VDS -30 V VGS = 0 V, ID = - 250 μA 2
Gate-Source Threshold Voltage VGS(th) -1.5 -2 -2.5 V VDS = VGS, ID = - 250 μA 2
Gate-Source Leakage IGSS -100 100 nA VDS = 0 V, VGS = ± 20 V 2
Zero Gate Voltage Drain Current IDSS -1 μA VGS = 0 V VDS = - 30 V 2
Zero Gate Voltage Drain Current IDSS -50 μA VGS = 0 V VDS = - 30 V, TJ = 125 °C 2
Zero Gate Voltage Drain Current IDSS -150 μA VGS = 0 V VDS = - 30 V, TJ = 175 °C 2
On-State Drain Current ID(on) -15 A VGS = - 10 V VDS- 5 V 2
Drain-Source On-State Resistance RDS(on) 0.056 0.075 Ω VGS = - 10 V ID = - 3.9 A 2
Drain-Source On-State Resistance RDS(on) 0.109 Ω VGS = - 10 V ID = - 3.9 A, TJ = 125 °C 2
Drain-Source On-State Resistance RDS(on) 0.127 Ω VGS = - 10 V ID = - 3.9 A, TJ = 175 °C 2
Drain-Source On-State Resistance RDS(on) 0.119 0.145 Ω VGS = - 4.5 V ID = - 2 A 2
Gate Resistance Rg 3.5 10.5 Ω f = 1 MHz 2
Input Capacitance Ciss 384 480 pF VGS = 0 V VDS = - 25 V, f = 1 MHz 2
Output Capacitance Coss 84 105 pF 2
Reverse Transfer Capacitance Crss 56 70 pF 2
Total Gate Charge Qg 9.5 15 nC VGS = - 10 V VDS = - 15 V, ID = - 4.9 A 2
Pulsed Current ISM -20 A Pulse test; pulse width 300 μs, duty cycle 2 % 2
Forward Voltage VSD -0.85 -1.2 V IF = - 3 A, VGS = 0 V 2
Rise Time tr 8 12 ns 2
Turn-Off Delay Time td(off) 15 23 ns 2
Fall Time tf 8 12 ns 2
Turn-On Delay Time td(on) 69 ns VDD = - 15 V, RL = 15, ID - 1 A, VGEN = - 10 V, Rg = 1 2
Forward Transconductance gfs 6 S VDS = - 15 V, ID = - 3.9 A 2
Gate-Source Charge Qgs 1.7 nC 2
Gate-Drain Charge Qgd 2.3 nC 2

CAD (KiCad official)

  • Symbol: SQ4937EY-T1_GE3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: sq4937ey-t1-ge3-etched.step / sq4937ey-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sq4937ey-t1-ge3.step / sq4937ey-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (9 pp, sha256 57e261be56f9e514, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF