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ESP32-S3R16V
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Espressif Systems RF and Wireless, 56-VFQFN Exposed Pad. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownESP32-S3R16V
Espressif Systems · RF and Wireless · 56-VFQFN Exposed Pad
ESP32-S3R16V from Espressif Systems, in a 56-VFQFN Exposed Pad. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LNA_IN | bidirectional | RF low-noise amplifier input/output signal pin. |
| 2 | VDD3P3 | power_in | Analog power domain supply pin. |
| 3 | VDD3P3 | power_in | Analog power domain supply pin. |
| 4 | CHIP_PU | input | High enables the chip and low disables it; the datasheet says this pin must not be left floating. |
| 5 | GPIO0 | bidirectional | General-purpose I/O with internal weak pull-up at reset; strapping pin for chip boot mode control. |
| 6 | GPIO1 | bidirectional | General-purpose I/O with ADC1_CH0 and TOUCH1 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 7 | GPIO2 | bidirectional | General-purpose I/O with ADC1_CH1 and TOUCH2 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 8 | GPIO3 | bidirectional | General-purpose I/O with ADC1_CH2 and TOUCH3 analog functions; floating at reset and used as a strapping pin for JTAG signal source selection. |
| 9 | GPIO4 | bidirectional | General-purpose I/O with ADC1_CH3 and TOUCH4 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 10 | GPIO5 | bidirectional | General-purpose I/O with ADC1_CH4 and TOUCH5 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 11 | GPIO6 | bidirectional | General-purpose I/O with ADC1_CH5 and TOUCH6 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 12 | GPIO7 | bidirectional | General-purpose I/O with ADC1_CH6 and TOUCH7 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 13 | GPIO8 | bidirectional | General-purpose I/O with ADC1_CH7 and TOUCH8 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 14 | GPIO9 | bidirectional | General-purpose I/O with ADC1_CH8 and TOUCH9 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 15 | GPIO10 | bidirectional | General-purpose I/O with ADC1_CH9 and TOUCH10 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 16 | GPIO11 | bidirectional | General-purpose I/O with ADC2_CH0 and TOUCH11 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 17 | GPIO12 | bidirectional | General-purpose I/O with ADC2_CH1 and TOUCH12 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 18 | GPIO13 | bidirectional | General-purpose I/O with ADC2_CH2 and TOUCH13 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 19 | GPIO14 | bidirectional | General-purpose I/O with ADC2_CH3 and TOUCH14 analog functions; shows a low-level glitch of about 60 µs at power-up. |
| 20 | VDD3P3_RTC | power_in | Power input for the RTC domain and part of the digital domain, which powers the RTC IO pins. |
| 21 | XTAL_32K_P | bidirectional | Positive terminal of the 32 kHz external clock oscillator; also general-purpose I/O RTC_GPIO15 with ADC2_CH4 and U0RTS. |
| 22 | XTAL_32K_N | bidirectional | Negative terminal of the 32 kHz external clock oscillator; also general-purpose I/O RTC_GPIO16 with ADC2_CH5 and U0CTS. |
| 23 | GPIO17 | bidirectional | General-purpose I/O with ADC2_CH6 and U1TXD; default drive strength is 10 mA. |
| 24 | GPIO18 | bidirectional | General-purpose I/O with ADC2_CH7 and U1RXD; default drive strength is 10 mA. |
| 25 | GPIO19 | bidirectional | General-purpose I/O, also USB_D- for the USB Serial/JTAG and USB OTG functions; default drive strength is 40 mA. |
| 26 | GPIO20 | bidirectional | General-purpose I/O, also USB_D+ for the USB Serial/JTAG and USB OTG functions; default drive strength is 40 mA. |
| 27 | GPIO21 | bidirectional | General-purpose I/O powered by VDD3P3_RTC with RTC_GPIO21 function. |
| 28 | SPICS1 | bidirectional | SPI chip select 1 for in-package PSRAM (GPIO26); powered by VDD_SPI, which is 1.8 V on R16V, and must not be used for other purposes. |
| 29 | VDD_SPI | power_out | Power pin for in-package memory and SPI IO; set to 1.8 V on the ESP32-S3R16V. |
| 30 | SPIHD | bidirectional | SPI hold signal for in-package flash/PSRAM (GPIO27) with internal weak pull-up at reset; powered by VDD_SPI. |
| 31 | SPIWP | bidirectional | SPI write-protect signal for in-package flash/PSRAM (GPIO28) with internal weak pull-up at reset; powered by VDD_SPI. |
| 32 | SPICS0 | bidirectional | SPI chip select 0 for in-package flash (GPIO29) with internal weak pull-up at reset; powered by VDD_SPI. |
| 33 | SPICLK | bidirectional | SPI clock for in-package flash/PSRAM (GPIO30) with internal weak pull-up at reset; powered by VDD_SPI. |
| 34 | SPIQ | bidirectional | SPI data line for in-package flash/PSRAM (GPIO31) with internal weak pull-up at reset; powered by VDD_SPI. |
| 35 | SPID | bidirectional | SPI data line for in-package flash/PSRAM (GPIO32) with internal weak pull-up at reset; powered by VDD_SPI. |
| 36 | SPICLK_N | bidirectional | Negative differential SPI clock (GPIO48) for in-package memory; at 1.8 V on R16V because VDD_SPI is 1.8 V. |
| 37 | SPICLK_P | bidirectional | Positive differential SPI clock (GPIO47) for in-package memory; at 1.8 V on R16V because VDD_SPI is 1.8 V. |
| 38 | GPIO33 | bidirectional | General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the high 4-bit data line for 8-line SPI mode when in-package Octal PSRAM is connected. |
| 39 | GPIO34 | bidirectional | General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ5 data line for in-package Octal PSRAM. |
| 40 | GPIO35 | bidirectional | General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ6 data line for in-package Octal PSRAM. |
| 41 | GPIO36 | bidirectional | General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQ7 data line for in-package Octal PSRAM. |
| 42 | GPIO37 | bidirectional | General-purpose I/O powered by VDD_SPI or VDD3P3_CPU; used as the DQS/DM strobe for in-package Octal PSRAM. |
| 43 | GPIO38 | bidirectional | General-purpose I/O powered by VDD3P3_CPU with FSPIWP and SUBSPIWP alternate functions. |
| 44 | MTCK | bidirectional | JTAG test clock (GPIO39) powered by VDD3P3_CPU; its weak pull-up depends on EFUSE_DIS_PAD_JTAG. |
| 45 | MTDO | bidirectional | JTAG test data output (GPIO40) powered by VDD3P3_CPU. |
| 46 | VDD3P3_CPU | power_in | Digital power domain supply for the digital IO pins. |
| 47 | MTDI | bidirectional | JTAG test data input (GPIO41) powered by VDD3P3_CPU. |
| 48 | MTMS | bidirectional | JTAG test mode select (GPIO42) powered by VDD3P3_CPU. |
| 49 | U0TXD | bidirectional | UART0 transmit data (GPIO43) with internal weak pull-up at reset; powered by VDD3P3_CPU. |
| 50 | U0RXD | bidirectional | UART0 receive data (GPIO44) with internal weak pull-up at reset; powered by VDD3P3_CPU. |
| 51 | GPIO45 | bidirectional | General-purpose I/O with internal weak pull-down at reset; strapping pin for VDD_SPI voltage control. |
| 52 | GPIO46 | bidirectional | General-purpose I/O with internal weak pull-down at reset; strapping pin for chip boot mode and ROM message printing control. |
| 53 | XTAL_N | passive | Negative terminal of the external clock input/output connected to the chip's crystal or oscillator. |
| 54 | XTAL_P | passive | Positive terminal of the external clock input/output connected to the chip's crystal or oscillator. |
| 55 | VDDA | power_in | Analog power domain supply pin. |
| 56 | VDDA | power_in | Analog power domain supply pin. |
| 57 | GND | power_in | Ground; the exposed pad of the QFN56 package is the external ground connection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Espressif Systems |
| Package | 56-VFQFN Exposed Pad |
| Category | RF and Wireless |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Allowed input voltage (input power pins) | -0.3 | 3.6 | V | 64 | |||
| Cumulative IO output current | Ioutput | 1500 | mA | 64 | |||
| Storage temperature | TSTORE | -40 | 150 | °C | 64 | ||
| Recommended input voltage | VDDA, VDD3P3 | 3 | 3.3 | 3.6 | V | 64 | |
| Recommended input voltage | VDD_SPI (as input) | 1.8 | 3.3 | 3.6 | V | 64 | |
| Cumulative input current | IVDD | 0.5 | A | 64 | |||
| ESD HBM (Human Body Model) | -2000 | 2000 | V | HBM, JS-001 | 69 | ||
| ESD CDM (Charge Device Model) | -1000 | 1000 | V | CDM, JS-002 | 69 | ||
| Latch-up current trigger | -200 | 200 | mA | JESD78, current trigger | 69 | ||
| Low-level input voltage | VIL | -0.3 | V | 65 | |||
| Chip reset voltage | VIL_nRST | -0.3 | V | CHIP_PU voltage is within the specified range | 65 | ||
| High-level input current | IIH | 50 | nA | 65 | |||
| Low-level input current | IIL | 50 | nA | 65 | |||
| Pin capacitance | CIN | 2 | pF | 65 | |||
| High-level source current | IOH | 40 | mA | VDD = 3.3 V, VOH >= 2.64 V, PAD_DRIVER = 3 | 65 | ||
| Low-level sink current | IOL | 28 | mA | VDD = 3.3 V, VOL = 0.495 V, PAD_DRIVER = 3 | 65 | ||
| Internal weak pull-up resistor | RPU | 45 | kΩ | 65 | |||
| Internal weak pull-down resistor | RPD | 45 | kΩ | 65 | |||
| VDD_SPI powered by VDD3P3_RTC via RSPI | RSPI | 14 | Ω | for 3.3 V flash/PSRAM | 65 | ||
| Output current when VDD_SPI powered by Flash Voltage Regulator | ISPI | 40 | mA | for 1.8 V flash/PSRAM | 65 | ||
| Differential nonlinearity | DNL | -4 | 4 | LSB | external 100 nF capacitor on ADC, 25 °C, Wi-Fi disabled | 66 | |
| Integral nonlinearity | INL | -8 | 8 | LSB | external 100 nF capacitor on ADC, 25 °C, Wi-Fi disabled | 66 | |
| ADC sampling rate | 100 | kSPS | 66 | ||||
| ADC total error ATTEN0 | -5 | 5 | mV | effective measurement range 0 ~ 850 | 66 | ||
| ADC total error ATTEN1 | -6 | 6 | mV | effective measurement range 0 ~ 1100 | 66 | ||
| ADC total error ATTEN2 | -10 | 10 | mV | effective measurement range 0 ~ 1600 | 66 | ||
| ADC total error ATTEN3 | -50 | 50 | mV | effective measurement range 0 ~ 2900 | 66 | ||
| Wi-Fi TX peak current 802.11b | 340 | mA | 802.11b, 1 Mbps, @21 dBm; 3.3 V, 25 °C | 66 | |||
| Wi-Fi TX peak current 802.11g | 291 | mA | 802.11g, 54 Mbps, @19 dBm; 3.3 V, 25 °C | 66 | |||
| Wi-Fi TX peak current 802.11n HT20 | 283 | mA | 802.11n, HT20, MCS7, @18.5 dBm; 3.3 V, 25 °C | 66 | |||
| Wi-Fi TX peak current 802.11n HT40 | 286 | mA | 802.11n, HT40, MCS7, @18 dBm; 3.3 V, 25 °C | 66 | |||
| Wi-Fi RX peak current 802.11b/g/n HT20 | 88 | mA | 802.11b/g/n, HT20; 3.3 V, 25 °C | 66 | |||
| Wi-Fi RX peak current 802.11n HT40 | 91 | mA | 802.11n, HT40; 3.3 V, 25 °C | 66 | |||
| Bluetooth LE TX peak current | 335 | mA | Bluetooth LE @ 21.0 dBm; 3.3 V, 25 °C | 67 | |||
| Bluetooth LE TX peak current | 176 | mA | Bluetooth LE @ 0 dBm; 3.3 V, 25 °C | 67 | |||
| Bluetooth LE RX peak current | 93 | mA | Bluetooth LE; 3.3 V, 25 °C | 67 | |||
| Light-sleep current | 240 | µA | VDD_SPI and Wi-Fi powered down, all GPIOs high-impedance | 68 | |||
| Deep-sleep current, ULP co-processor on (ULP-FSM) | 170 | µA | ULP co-processor powered on | 68 | |||
| Deep-sleep current, ULP co-processor on (ULP-RISC-V) | 190 | µA | ULP co-processor powered on | 68 | |||
| Deep-sleep current, ULP sensor-monitored pattern | 18 | µA | ULP sensor-monitored pattern | 68 | |||
| Deep-sleep current, RTC memory and RTC peripherals powered up | 8 | µA | RTC memory and RTC peripherals powered up | 68 | |||
| Deep-sleep current, RTC memory powered up, RTC peripherals down | 7 | µA | RTC memory powered up, RTC peripherals powered down | 68 | |||
| Power-off current | 1 | µA | CHIP_PU set to low level | 68 | |||
| Flash power supply voltage (1.8 V) | VCC | 1.65 | 1.8 | 2 | V | Power supply voltage (1.8 V) | 68 |
| Flash maximum clock frequency | FC | 80 | MHz | 68 | |||
| PSRAM power supply voltage (1.8 V) | VCC | 1.62 | 1.8 | 1.98 | V | Power supply voltage (1.8 V) | 69 |
CAD (KiCad official)
- Symbol:
ESP32-S3R16V - Footprint:
Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP5.6x5.6mm - 3D model: 56-VFQFN Exposed Pad (KiCad packages3D, STEP)
- 3D model files:
esp32-s3r16v-etched.step/esp32-s3r16v-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);esp32-s3r16v.step/esp32-s3r16v.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Espressif Systems datasheet (87 pp, sha256
2d5a7cb7fd559d8d, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).