LM43602AQPWPRQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SW	power_out	Switching output of the regulator, internally connected to both power MOSFETs, connects to the power inductor.
2	SW	power_out	Switching output of the regulator, internally connected to both power MOSFETs, connects to the power inductor.
3	CBOOT	passive	Boot-strap capacitor connection for the high-side driver; connect a high quality 470-nF capacitor from CBOOT to SW.
4	VCC	power_out	Internal bias supply output for bypassing; connect a bypass capacitor to AGND, do not load it externally, and never short it to ground during operation.
5	BIAS	power_in	Optional internal LDO supply input, recommended tied to VOUT for 3.3 V ≤ VOUT ≤ 28 V; BIAS voltage should not exceed VIN and the bypass capacitor is 1 to 10 µF, or tied to ground when not used.
6	SYNC	input	Clock input to synchronize switching to an external clock, requires proper high speed termination and is connected to ground if not used.
7	RT	passive	Connect a resistor RT from this pin to AGND to program the switching frequency; leave floating for the 500 kHz default.
8	PGOOD	output	Open drain power-good flag output, requires a 10 kΩ to 100 kΩ pullup to a DC rail no higher than 12 V.
9	FB	input	Feedback sense input connected to the midpoint of the feedback divider to set VOUT; do not short to ground during operation.
10	AGND	power_in	Analog ground pin serving as the ground reference for internal references and logic, connected to system ground.
11	SS/TRK	passive	Soft-start control pin: leave floating for internal soft-start, connect a capacitor to extend soft-start time, or connect an external voltage ramp for tracking.
12	EN	input	Enable input to the internal LDO and regulator, high = ON and low = OFF, must not be left floating.
13	VIN	power_in	Supply input to the internal LDO and high side power FET, requires bypass capacitor CIN placed as close as possible to the VIN and PGND pins; the datasheet gives a 3.5 V to 36 V recommended input range.
14	VIN	power_in	Supply input to the internal LDO and high side power FET, requires bypass capacitor CIN placed as close as possible to the VIN and PGND pins; the datasheet gives a 3.5 V to 36 V recommended input range.
15	PGND	power_in	Power ground pin connected internally to the low side power FET, connects to system ground, PAD, AGND and the CIN and COUT grounds with a short path to CIN.
16	PGND	power_in	Power ground pin connected internally to the low side power FET, connects to system ground, PAD, AGND and the CIN and COUT grounds with a short path to CIN.
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-16-EP
Category	Power Management (PMIC)
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VIN to PGND	VIN	-0.3		42	V		4
EN to PGND	EN	-0.3			V	upper limit printed as VIN + 0.3	4
FB, RT, SS/TRK to AGND		-0.3		3.6	V		4
PGOOD to AGND		-0.3		15	V		4
SYNC to AGND		-0.3		5.5	V		4
BIAS to AGND		-0.3		30	V	or VIN	4
AGND to PGND		-0.3		0.3	V		4
SW to PGND		-0.3			V	upper limit printed as VIN + 0.3	4
SW to PGND less than 10-ns transients		-3.5		42	V		4
CBOOT to SW		-0.3		5.5	V		4
VCC to AGND	VCC	-0.3		3.6	V		4
Storage temperature	Tstg	-65		150	°C		4
Operating junction temperature (absolute maximum)		-40		150	°C		4
VIN to PGND (recommended)	VIN	3.5		36	V		4
EN (recommended)	EN	-0.3			V	upper limit printed as VIN	4
FB (recommended)		-0.3		1.1	V		4
PGOOD (recommended)		-0.3		12	V		4
BIAS input not used		-0.3		0.3	V		4
BIAS input used		3.3		28	V	or VIN	4
AGND to PGND (recommended)		-0.1		0.1	V		4
Output voltage	VOUT	1		28	V		4
Output current	IOUT	0		2	A		4
Operating junction temperature (recommended)	TJ	-40		125	°C		4
Feedback voltage	VFB	1.012	1.015	1.019	V	TJ = 25ºC	6
Feedback voltage	VFB	0.999	1.015	1.032	V	TJ = -40ºC to 125 ºC	6
Input leakage current at FB pin	ILKG-FB		0.2	65	nA	FB = 1.015 V	6
Peak inductor current limit	IHS-LIMIT	3.65	4.5	5.15	A		6
Inductor current valley limit	ILS-LIMIT	1.75	2	2.25	A		6
Soft-start charge current	ISSC	1.25	2	2.75	µA		6
Power-good flag over voltage tripping threshold		110		113	% of FB voltage		6
Power-good flag under voltage tripping threshold		77		88	% of FB voltage		6
Internal LDO input change over threshold to BIAS (rising)	VBIAS-ON	2.94		3.18	V	VBIAS rising threshold	5
Enable input leakage current	ILKG-EN		0.85	1.75	µA	VEN = 3.3 V	5
Shutdown quiescent current	ISHDN		1.2	3.1	µA	VEN = 0 V	5
Operating quiescent current (non-switching) from VIN	IQ-NONSW		5	10	µA	VEN = 3.3 V, VFB = 1.5 V, VBIAS = 3.4 V external	5
Operating quiescent current (non-switching) from external VBIAS	IBIAS-NONSW		85	130	µA	VEN = 3.3 V, VFB = 1.5 V, VBIAS = 3.4 V external	5
Precision enable level for switching and regulator output VOUT	VEN-VOUT-H	2	2.2	2.42	V	VENABLE high level	5
PGOOD pin pulldown resistance when power bad	RPGOOD	69		150	Ω	VEN = 3.3 V	6
PGOOD pin pulldown resistance when power bad	RPGOOD	150		350	Ω	VEN = 0 V	6
Oscillator default frequency	FOSC-DEFAULT	425	500	580	kHz	RT pin open circuit	7
Minimum adjustable frequency	FADJ	200			kHz	With 1% resistors at RT pin	7
Maximum adjustable frequency	FADJ			2200	kHz		7
Sync clock high level threshold	VSYNC-HIGH	2			V		7
Sync clock low level threshold	VSYNC-LOW			0.4	V		7
Sync clock maximum duty cycle	DSYNC-MAX			90	%		7
Minimum high side MOSFET ON time	tON-MIN		125	165	ns		7
Minimum high side MOSFET OFF time	tOFF-MIN		200	250	ns		7
Hiccup retry delay time	TOC		5.5		ms		6
Junction-to-ambient thermal resistance	RθJA		38.9		°C/W	PWP HTSSOP 16 pins, 4-layer JEDEC board	5
Junction-to-case (bottom) thermal resistance	RθJC(bot)		1.7		°C/W		5
Operating quiescent current (switching)	IQ-SW		27		µA	VEN = 3.3 V, IOUT = 0 A, RT = open, VBIAS = VOUT = 3.3 V, RFBT = 1 Meg	5
Voltage level to enable the internal LDO output VCC	VEN-VCC-H		1.2		V	VENABLE high level	5
Voltage level to disable the internal LDO output VCC	VEN-VCC-L		0.525		V	VENABLE low level	5
Internal LDO output voltage VCC	VCC		3.28		V	VIN ≥ 3.8 V	5
UVLO threshold for VCC rising	VCC-UVLO		3.1		V	VCC rising threshold	5
Minimum input voltage for startup	VIN-MIN-ST		3.8		V		5
Thermal shutdown threshold	TSD		160		°C		6
High-side MOSFET ON resistance	RDS-ON-HS		120		mΩ	IOUT = 1 A, VBIAS = VOUT = 3.3 V	6
Low-side MOSFET ON resistance	RDS-ON-LS		65		mΩ	IOUT = 1 A, VBIAS = VOUT = 3.3 V	6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours (shapes) high curr	34

CAD (KiCad official)

Symbol: LM43602AQPWPRQ1
Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
3D model files: lm43602aqpwprq1-etched.step / lm43602aqpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm43602aqpwprq1.step / lm43602aqpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (44 pp, sha256 93411b2243eed0ae, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LM43602AQPWPRQ1

Verified LM43602AQPWPRQ1

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README