component
74HC08D-Q100
Public Made by Adomby adom
Nexperia Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdown74HC08D-Q100
Nexperia · Logic Gates · SOP-14
74HC08D-Q100 from Nexperia, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of the first 2-input AND gate; input voltage range is 0 V to VCC. |
| 2 | 1B | input | Data input 1B of the first 2-input AND gate; input voltage range is 0 V to VCC. |
| 3 | 1Y | output | Data output 1Y of the first AND gate (1Y = 1A AND 1B); output voltage range is 0 V to VCC. |
| 4 | 2A | input | Data input 2A of the second 2-input AND gate; input voltage range is 0 V to VCC. |
| 5 | 2B | input | Data input 2B of the second 2-input AND gate; input voltage range is 0 V to VCC. |
| 6 | 2Y | output | Data output 2Y of the second AND gate (2Y = 2A AND 2B); output voltage range is 0 V to VCC. |
| 7 | GND | power_in | Ground pin at 0 V; all voltages are referenced to this pin. |
| 8 | 3Y | output | Data output 3Y of the third AND gate (3Y = 3A AND 3B); output voltage range is 0 V to VCC. |
| 9 | 3A | input | Data input 3A of the third 2-input AND gate; input voltage range is 0 V to VCC. |
| 10 | 3B | input | Data input 3B of the third 2-input AND gate; input voltage range is 0 V to VCC. |
| 11 | 4Y | output | Data output 4Y of the fourth AND gate (4Y = 4A AND 4B); output voltage range is 0 V to VCC. |
| 12 | 4A | input | Data input 4A of the fourth 2-input AND gate; input voltage range is 0 V to VCC. |
| 13 | 4B | input | Data input 4B of the fourth 2-input AND gate; input voltage range is 0 V to VCC. |
| 14 | VCC | power_in | Supply voltage; 2.0 V to 6.0 V recommended for the 74HC08-Q100 (4.5 V to 5.5 V for the 74HCT08-Q100 variant). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
74HC08D-Q100 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
74hc08d-q100-etched.step/74hc08d-q100-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc08d-q100.step/74hc08d-q100.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (13 pp, sha256
6f32abaec1b6f0ca, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).