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CDCE62005RGZT
Public Made by Adomby adom
Texas Instruments Clock Generators / Frequency Synthesizers / PLL, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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README
markdownCDCE62005RGZT
Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · VQFN-48-EP(7x7)
CDCE62005RGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC_IN_SEC | power_in | 3.3-V supply for the secondary reference input buffer and circuitry. |
| 2 | SEC_REF- | input | Universal input buffer (LVPECL, LVDS) negative input for the secondary reference clock; for LVCMOS on SEC_REF+, connect through a 1-kΩ resistor to GND. |
| 3 | SEC_REF+ | input | Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the secondary reference clock. |
| 4 | REG_CAP1 | passive | Capacitor for the internal regulator; connect a 10-µF capacitor (X5R or X7R). |
| 5 | VCC1_PLL | power_in | 3.3-V PLL supply voltage for the PLL circuitry (filter required). |
| 6 | U4P | output | Positive side of output 4, configurable as LVPECL, LVDS or LVCMOS via SPI, with EEPROM-configurable power-up setting. |
| 7 | U4N | output | Negative side of output 4, configurable as LVPECL, LVDS or LVCMOS via SPI, with EEPROM-configurable power-up setting. |
| 8 | VCC_OUT | power_in | 3.3-V supply for the output buffers and output dividers. |
| 9 | U3P | output | Positive side of output 3, configurable as LVPECL, LVDS or LVCMOS via SPI, with EEPROM-configurable power-up setting. |
| 10 | U3N | output | Negative side of output 3, configurable as LVPECL, LVDS or LVCMOS via SPI, with EEPROM-configurable power-up setting. |
| 11 | VCC_OUT | power_in | 3.3-V supply for the output buffers and output dividers. |
| 12 | Power_Down | input | Active-low power-down control with internal 150-kΩ pull-up (defaults to logic 1); SPI_LE must be high at the rising edge to load the EEPROM. |
| 13 | AUX OUT | output | Auxiliary LVCMOS output programmable via SPI to be driven by Output 2 or Output 3. |
| 14 | SYNC | input | Active-low sync mode control with internal 150-kΩ pull-up (defaults to logic 1). |
| 15 | VCC_AUXOUT | power_in | 3.3-V supply for the AUX_OUT circuitry. |
| 16 | U2P | output | Positive side of output 2, configurable as LVPECL, LVDS or LVCMOS via SPI, with EEPROM-configurable power-up setting. |
| 17 | U2N | output | Negative side of output 2, configurable as LVPECL, LVDS or LVCMOS via SPI, with EEPROM-configurable power-up setting. |
| 18 | VCC_OUT | power_in | 3.3-V supply for the output buffers and output dividers. |
| 19 | U1P | output | Positive side of output 1, configurable as LVPECL, LVDS or LVCMOS via SPI, with EEPROM-configurable power-up setting. |
| 20 | U1N | output | Negative side of output 1, configurable as LVPECL, LVDS or LVCMOS via SPI, with EEPROM-configurable power-up setting. |
| 21 | VCC_OUT | power_in | 3.3-V supply for the output buffers and output dividers. |
| 22 | SPI_MISO | tri_state | 3-state LVCMOS output enabled when SPI_LE is asserted low; serial data output to the SPI bus interface. |
| 23 | SPI_MOSI | input | LVCMOS serial control data input (Master Out Slave In) for the SPI bus, with internal 150-kΩ pull-up (defaults to logic 1). |
| 24 | SPI_CLK | input | LVCMOS serial control clock input for the SPI bus with hysteresis and internal 150-kΩ pull-up (defaults to logic 1). |
| 25 | SPI_LE | input | LVCMOS SPI latch enable with hysteresis and internal 150-kΩ pull-up; must be logic 1 before Power_Down goes low-to-high for the EEPROM to load properly. |
| 26 | VCC_OUT | power_in | 3.3-V supply for the output buffers and output dividers. |
| 27 | U0P | output | Positive side of output 0, configurable as LVPECL, LVDS or LVCMOS via SPI, with EEPROM-configurable power-up setting. |
| 28 | U0N | output | Negative side of output 0, configurable as LVPECL, LVDS or LVCMOS via SPI, with EEPROM-configurable power-up setting. |
| 29 | VCC_OUT | power_in | 3.3-V supply for the output buffers and output dividers. |
| 30 | TESTOUTA | passive | Reserved analog pin; pull down to GND via a 1-kΩ resistor. |
| 31 | REF_SEL | input | External reference select when Auto Reference Select is off (1: PRI_REF, 0: SEC_REF), with internal 150-kΩ pull-up; ignored when auto select is on. |
| 32 | VCC_OUT | power_in | 3.3-V supply for the output buffers and output dividers. |
| 33 | TEST_MODE | input | Test mode pin that should be tied high or left unconnected. |
| 34 | VCC_VCO | power_in | 3.3-V VCO input buffer and circuitry supply voltage (filter required). |
| 35 | VCC_VCO | power_in | 3.3-V VCO input buffer and circuitry supply voltage (filter required). |
| 36 | GND_VCO | power_in | Ground that connects to VCO ground (shorted to GND). |
| 37 | PLL_LOCK | output | Output that indicates PLL lock status. |
| 38 | REG_CAP2 | passive | Capacitor for the internal regulator; connect a 10-µF capacitor (X5R or X7R). |
| 39 | VCC2_PLL | power_in | 3.3-V PLL supply voltage for the PLL circuitry (filter required). |
| 40 | EXT_LFP | passive | External loop filter input, positive. |
| 41 | EXT_LFN | passive | External loop filter input, negative. |
| 42 | VCC2_PLL | power_in | 3.3-V PLL supply voltage for the PLL circuitry (filter required). |
| 43 | AUX IN | input | Single-ended auxiliary input including an on-board oscillator circuit so a crystal may be connected. |
| 44 | VCC_AUXIN | power_in | 3.3-V supply for the crystal oscillator input circuitry. |
| 45 | PRI_REF+ | input | Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the primary reference clock. |
| 46 | PRI_REF- | input | Universal input buffer (LVPECL, LVDS) negative input for the primary reference clock; for LVCMOS on PRI_REF+, connect through a 1-kΩ resistor to GND. |
| 47 | VCC_IN_PRI | power_in | 3.3-V supply for the primary reference input buffer and circuitry. |
| 48 | VBB | passive | Capacitor for the internal termination voltage; connect a 1-µF capacitor (X5R or X7R). |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Clock and Timing |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
CDCE62005RGZT - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
cdce62005rgzt-etched.step/cdce62005rgzt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdce62005rgzt.step/cdce62005rgzt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (85 pp, sha256
25f7bd77e1d2f7ec, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).