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DS42MB200TSQ
Public Made by Adomby adom
Texas Instruments Signal Buffers, Repeaters, Splitters, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownDS42MB200TSQ
Texas Instruments · Signal Buffers, Repeaters, Splitters · WQFN-48-EP(7x7)
DS42MB200TSQ from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PREL_1 | input | Selects bit 1 of the line-side driver pre-emphasis level for LO_1± per Table 3 (0, −3, −6, −9 dB); internally pulled high. |
| 2 | VCC | power_in | Supply pin, VCC = 3.3V ±5% (3.135 V to 3.465 V); connect through a low-inductance path and bypass with a 0.01 µF or 0.1 µF X7R size-0402 capacitor to the ground plane. |
| 3 | SOB_0- | output | Inverting differential output of mux_0 at the switch-B side, with an internal 50Ω termination to VCC. |
| 4 | SOB_0+ | output | Non-inverting differential output of mux_0 at the switch-B side, with an internal 50Ω termination to VCC. |
| 5 | GND | power_in | Ground reference pin; connect to the ground plane through a low-inductance path with a via placed close to the pad. |
| 6 | LI_0+ | input | Non-inverting differential input of port 0 at the line side, with an internal 50Ω to an internal reference voltage (AC-coupled, self-biased about 1.5 V). |
| 7 | LI_0- | input | Inverting differential input of port 0 at the line side, with an internal 50Ω to an internal reference voltage (AC-coupled, self-biased about 1.5 V). |
| 8 | VCC | power_in | Supply pin, VCC = 3.3V ±5% (3.135 V to 3.465 V); connect through a low-inductance path and bypass with a 0.01 µF or 0.1 µF X7R size-0402 capacitor to the ground plane. |
| 9 | LO_1+ | output | Non-inverting differential output of port 1 at the line side, with an internal 50Ω termination to VCC. |
| 10 | LO_1- | output | Inverting differential output of port 1 at the line side, with an internal 50Ω termination to VCC. |
| 11 | GND | power_in | Ground reference pin; connect to the ground plane through a low-inductance path with a via placed close to the pad. |
| 12 | PREL_0 | input | Selects bit 0 of the line-side driver pre-emphasis level for LO_0± per Table 3 (0, −3, −6, −9 dB); internally pulled high. |
| 13 | MUX_S1 | input | 3.3V LVCMOS control: logic low selects SIB_1± for mux_1, default (high, internally pulled high) selects SIA_1±. |
| 14 | VCC | power_in | Supply pin, VCC = 3.3V ±5% (3.135 V to 3.465 V); connect through a low-inductance path and bypass with a 0.01 µF or 0.1 µF X7R size-0402 capacitor to the ground plane. |
| 15 | SIA_1- | input | Inverting differential input to mux_1 at the switch-A side, with an internal 50Ω to an internal reference voltage. |
| 16 | SIA_1+ | input | Non-inverting differential input to mux_1 at the switch-A side, with an internal 50Ω to an internal reference voltage. |
| 17 | GND | power_in | Ground reference pin; connect to the ground plane through a low-inductance path with a via placed close to the pad. |
| 18 | SIB_1- | input | Inverting differential input to mux_1 at the switch-B side, with an internal 50Ω to an internal reference voltage. |
| 19 | SIB_1+ | input | Non-inverting differential input to mux_1 at the switch-B side, with an internal 50Ω to an internal reference voltage. |
| 20 | VCC | power_in | Supply pin, VCC = 3.3V ±5% (3.135 V to 3.465 V); connect through a low-inductance path and bypass with a 0.01 µF or 0.1 µF X7R size-0402 capacitor to the ground plane. |
| 21 | SOA_1- | output | Inverting differential output of mux_1 at the switch-A side, with an internal 50Ω termination to VCC. |
| 22 | SOA_1+ | output | Non-inverting differential output of mux_1 at the switch-A side, with an internal 50Ω termination to VCC. |
| 23 | LB1A | input | A logic low enables the internal loopback from SIA_1± to SOA_1±; internally pulled high (normal mode, loopback disabled). |
| 24 | LB1B | input | A logic low enables the internal loopback from SIB_1± to SOB_1±; internally pulled high (normal mode, loopback disabled). |
| 25 | PRES_1 | input | Selects bit 0 of the switch-side driver pre-emphasis level for SOA_1±, SOB_1± per Table 4 (0, −3, −6, −9 dB); internally pulled high. |
| 26 | RSV | input | Reserved pin for factory testing; may be left open or tied to GND directly or through a pull-down resistor. |
| 27 | SOB_1- | output | Inverting differential output of mux_1 at the switch-B side, with an internal 50Ω termination to VCC. |
| 28 | SOB_1+ | output | Non-inverting differential output of mux_1 at the switch-B side, with an internal 50Ω termination to VCC. |
| 29 | VCC | power_in | Supply pin, VCC = 3.3V ±5% (3.135 V to 3.465 V); connect through a low-inductance path and bypass with a 0.01 µF or 0.1 µF X7R size-0402 capacitor to the ground plane. |
| 30 | LI_1+ | input | Non-inverting differential input of port 1 at the line side, with an internal 50Ω to an internal reference voltage (AC-coupled, self-biased about 1.5 V). |
| 31 | LI_1- | input | Inverting differential input of port 1 at the line side, with an internal 50Ω to an internal reference voltage (AC-coupled, self-biased about 1.5 V). |
| 32 | GND | power_in | Ground reference pin; connect to the ground plane through a low-inductance path with a via placed close to the pad. |
| 33 | LO_0+ | output | Non-inverting differential output of port 0 at the line side, with an internal 50Ω termination to VCC. |
| 34 | LO_0- | output | Inverting differential output of port 0 at the line side, with an internal 50Ω termination to VCC. |
| 35 | VCC | power_in | Supply pin, VCC = 3.3V ±5% (3.135 V to 3.465 V); connect through a low-inductance path and bypass with a 0.01 µF or 0.1 µF X7R size-0402 capacitor to the ground plane. |
| 36 | PRES_0 | input | Selects bit 1 of the switch-side driver pre-emphasis level for SOA_0±, SOB_0± per Table 4 (0, −3, −6, −9 dB); internally pulled high. |
| 37 | MUX_S0 | input | 3.3V LVCMOS control: logic low selects SIB_0± for mux_0, default (high, internally pulled high) selects SIA_0±. |
| 38 | VCC | power_in | Supply pin, VCC = 3.3V ±5% (3.135 V to 3.465 V); connect through a low-inductance path and bypass with a 0.01 µF or 0.1 µF X7R size-0402 capacitor to the ground plane. |
| 39 | SIA_0- | input | Inverting differential input to mux_0 at the switch-A side, with an internal 50Ω to an internal reference voltage. |
| 40 | SIA_0+ | input | Non-inverting differential input to mux_0 at the switch-A side, with an internal 50Ω to an internal reference voltage. |
| 41 | GND | power_in | Ground reference pin; connect to the ground plane through a low-inductance path with a via placed close to the pad. |
| 42 | SIB_0- | input | Inverting differential input to mux_0 at the switch-B side, with an internal 50Ω to an internal reference voltage. |
| 43 | SIB_0+ | input | Non-inverting differential input to mux_0 at the switch-B side, with an internal 50Ω to an internal reference voltage. |
| 44 | VCC | power_in | Supply pin, VCC = 3.3V ±5% (3.135 V to 3.465 V); connect through a low-inductance path and bypass with a 0.01 µF or 0.1 µF X7R size-0402 capacitor to the ground plane. |
| 45 | SOA_0- | output | Inverting differential output of mux_0 at the switch-A side, with an internal 50Ω termination to VCC. |
| 46 | SOA_0+ | output | Non-inverting differential output of mux_0 at the switch-A side, with an internal 50Ω termination to VCC. |
| 47 | LB0A | input | A logic low enables the internal loopback from SIA_0± to SOA_0±; internally pulled high (normal mode, loopback disabled). |
| 48 | LB0B | input | A logic low enables the internal loopback from SIB_0± to SOB_0±; internally pulled high (normal mode, loopback disabled). |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
DS42MB200TSQ - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
ds42mb200tsq-etched.step/ds42mb200tsq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds42mb200tsq.step/ds42mb200tsq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (17 pp, sha256
01f3096e8156eae0, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).