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MK10DN32VFM5

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by adom

NXP Semicon Pre-ordered MCUs, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersmk10dn32vfm5factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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MK10DN32VFM5

NXP Semicon · Pre-ordered MCUs · QFN-32-EP(5x5)

MK10DN32VFM5 from NXP Semicon, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Digital supply input, device operating range 1.71 to 3.6 V.
2 VSS power_in Digital ground.
3 PTE16 bidirectional GPIO PTE16 (ALT1) with default ADC0_SE4a, also SPI0_PCS0, UART2_TX, FTM_CLKIN0 and FTM0_FLT3.
4 PTE17 bidirectional GPIO PTE17 (ALT1) with default ADC0_SE5a, also SPI0_SCK, UART2_RX, FTM_CLKIN1 and LPTMR0_ALT3.
5 PTE18 bidirectional GPIO PTE18 (ALT1) with default ADC0_SE6a, also SPI0_SOUT, UART2_CTS_b and I2C0_SDA.
6 PTE19 bidirectional GPIO PTE19 (ALT1) with default ADC0_SE7a, also SPI0_SIN, UART2_RTS_b and I2C0_SCL.
7 VDDA power_in Analog supply input.
8 VSSA power_in Analog ground.
9 XTAL32 output 32 kHz crystal oscillator output (XTAL32).
10 EXTAL32 input 32 kHz crystal oscillator input (EXTAL32).
11 VBAT power_in Battery backup supply input (VBAT).
12 PTA0 bidirectional GPIO PTA0 (ALT1) with default JTAG_TCLK/SWD_CLK/EZP_CLK, also TSI0_CH1, UART0_CTS_b/UART0_COL_b and FTM0_CH5.
13 PTA1 bidirectional GPIO PTA1 (ALT1) with default JTAG_TDI/EZP_DI, also TSI0_CH2, UART0_RX and FTM0_CH6.
14 PTA2 bidirectional GPIO PTA2 (ALT1) with default JTAG_TDO/TRACE_SWO/EZP_DO, also TSI0_CH3, UART0_TX and FTM0_CH7.
15 PTA3 bidirectional GPIO PTA3 (ALT1) with default JTAG_TMS/SWD_DIO, also TSI0_CH4, UART0_RTS_b and FTM0_CH0.
16 PTA4/LLWU_P3 bidirectional GPIO PTA4 with LLWU_P3 wakeup input, default NMI_b/EZP_CS_b, also TSI0_CH5 and FTM0_CH1.
17 PTA18 bidirectional GPIO PTA18 (ALT1) with default EXTAL0 (oscillator input), also FTM0_FLT2 and FTM_CLKIN0.
18 PTA19 bidirectional GPIO PTA19 (ALT1) with default XTAL0 (oscillator), also FTM1_FLT0, FTM_CLKIN1 and LPTMR0_ALT1.
19 RESET_b bidirectional External reset pin (RESET_b).
20 PTB0/LLWU_P5 bidirectional GPIO PTB0 with LLWU_P5 wakeup input, default ADC0_SE8/TSI0_CH0, also I2C0_SCL, FTM1_CH0 and FTM1_QD_PHA.
21 PTB1 bidirectional GPIO PTB1 (ALT1) with default ADC0_SE9/TSI0_CH6, also I2C0_SDA, FTM1_CH1 and FTM1_QD_PHB.
22 PTC1/LLWU_P6 bidirectional GPIO PTC1 with LLWU_P6 wakeup input, default ADC0_SE15/TSI0_CH14, also SPI0_PCS3, UART1_RTS_b, FTM0_CH0 and I2S0_TXD0.
23 PTC2 bidirectional GPIO PTC2 (ALT1) with default ADC0_SE4b/CMP1_IN0/TSI0_CH15, also SPI0_PCS2, UART1_CTS_b, FTM0_CH1 and I2S0_TX_FS.
24 PTC3/LLWU_P7 bidirectional GPIO PTC3 with LLWU_P7 wakeup input, default CMP1_IN1, also SPI0_PCS1, UART1_RX, FTM0_CH2 and I2S0_TX_BCLK.
25 PTC4/LLWU_P8 bidirectional GPIO PTC4 with LLWU_P8 wakeup input (default disabled), also SPI0_PCS0, UART1_TX, FTM0_CH3 and CMP1_OUT.
26 PTC5/LLWU_P9 bidirectional GPIO PTC5 with LLWU_P9 wakeup input (default disabled), also SPI0_SCK, LPTMR0_ALT2, I2S0_RXD0 and CMP0_OUT.
27 PTC6/LLWU_P10 bidirectional GPIO PTC6 with LLWU_P10 wakeup input, default CMP0_IN0, also SPI0_SOUT, PDB0_EXTRG, I2S0_RX_BCLK and I2S0_MCLK.
28 PTC7 bidirectional GPIO PTC7 (ALT1) with default CMP0_IN1, also SPI0_SIN and I2S0_RX_FS.
29 PTD4/LLWU_P14 bidirectional GPIO PTD4 with LLWU_P14 wakeup input (default disabled), also SPI0_PCS1, UART0_RTS_b, FTM0_CH4 and EWM_IN.
30 PTD5 bidirectional GPIO PTD5 (ALT1) with default ADC0_SE6b, also SPI0_PCS2, UART0_CTS_b/UART0_COL_b, FTM0_CH5 and EWM_OUT_b.
31 PTD6/LLWU_P15 bidirectional GPIO PTD6 with LLWU_P15 wakeup input, default ADC0_SE7b, also SPI0_PCS3, UART0_RX, FTM0_CH6 and FTM0_FLT0.
32 PTD7 bidirectional GPIO PTD7 (ALT1, default disabled), also CMT_IRO, UART0_TX, FTM0_CH7 and FTM0_FLT1.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package QFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

CAD (KiCad official)

  • Symbol: MK10DN32VFM5
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: mk10dn32vfm5-etched.step / mk10dn32vfm5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mk10dn32vfm5.step / mk10dn32vfm5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (57 pp, sha256 d6d66b6075c58aa6, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF