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CD74HCT11M96
Public Made by Adomby adom
Texas Instruments Logic ICs, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD74HCT11M96
Texas Instruments · Logic ICs · SOIC-14
CD74HCT11M96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of gate 1 of the triple 3-input AND gate; HCT inputs are LSTTL-compatible with VIL 0.8 V (max) and VIH 2 V (min). |
| 2 | 1B | input | Input B of gate 1 of the triple 3-input AND gate; HCT inputs are LSTTL-compatible with VIL 0.8 V (max) and VIH 2 V (min). |
| 3 | 2A | input | Input A of gate 2 of the triple 3-input AND gate; HCT inputs are LSTTL-compatible with VIL 0.8 V (max) and VIH 2 V (min). |
| 4 | 2B | input | Input B of gate 2 of the triple 3-input AND gate; HCT inputs are LSTTL-compatible with VIL 0.8 V (max) and VIH 2 V (min). |
| 5 | 2C | input | Input C of gate 2 of the triple 3-input AND gate; HCT inputs are LSTTL-compatible with VIL 0.8 V (max) and VIH 2 V (min). |
| 6 | 2Y | output | Output of gate 2 (high only when 2A, 2B and 2C are all high); standard outputs drive 10 LSTTL loads. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | output | Output of gate 3 (high only when 3A, 3B and 3C are all high); standard outputs drive 10 LSTTL loads. |
| 9 | 3A | input | Input A of gate 3 of the triple 3-input AND gate; HCT inputs are LSTTL-compatible with VIL 0.8 V (max) and VIH 2 V (min). |
| 10 | 3B | input | Input B of gate 3 of the triple 3-input AND gate; HCT inputs are LSTTL-compatible with VIL 0.8 V (max) and VIH 2 V (min). |
| 11 | 3C | input | Input C of gate 3 of the triple 3-input AND gate; HCT inputs are LSTTL-compatible with VIL 0.8 V (max) and VIH 2 V (min). |
| 12 | 1Y | output | Output of gate 1 (high only when 1A, 1B and 1C are all high); standard outputs drive 10 LSTTL loads. |
| 13 | 1C | input | Input C of gate 1 of the triple 3-input AND gate; HCT inputs are LSTTL-compatible with VIL 0.8 V (max) and VIH 2 V (min). |
| 14 | VCC | power_in | Supply voltage; HCT types operate from 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High Level Input Voltage (25°C) | VIH | 2 | V | VCC=4.5 to 5.5V (HCT) | 4 | ||
| High Level Input Voltage (-40°C to 85°C) | VIH | 2 | V | VCC=4.5 to 5.5V (HCT) | 4 | ||
| High Level Input Voltage (-55°C to 125°C) | VIH | 2 | V | VCC=4.5 to 5.5V (HCT) | 4 | ||
| Low Level Input Voltage (25°C) | VIL | 0.8 | V | VCC=4.5 to 5.5V (HCT) | 4 | ||
| Low Level Input Voltage (-40°C to 85°C) | VIL | 0.8 | V | VCC=4.5 to 5.5V (HCT) | 4 | ||
| Low Level Input Voltage (-55°C to 125°C) | VIL | 0.8 | V | VCC=4.5 to 5.5V (HCT) | 4 | ||
| High Level Output Voltage CMOS Loads (25°C) | VOH | 4.4 | V | IO=-0.02mA; VI=VIH or VIL; VCC=4.5V | 4 | ||
| High Level Output Voltage CMOS Loads (-40°C to 85°C) | VOH | 4.4 | V | IO=-0.02mA; VI=VIH or VIL; VCC=4.5V | 4 | ||
| High Level Output Voltage CMOS Loads (-55°C to 125°C) | VOH | 4.4 | V | IO=-0.02mA; VI=VIH or VIL; VCC=4.5V | 4 | ||
| High Level Output Voltage TTL Loads (25°C) | VOH | 3.98 | V | IO=-4mA; VCC=4.5V | 4 | ||
| High Level Output Voltage TTL Loads (-40°C to 85°C) | VOH | 3.84 | V | IO=-4mA; VCC=4.5V | 4 | ||
| High Level Output Voltage TTL Loads (-55°C to 125°C) | VOH | 3.7 | V | IO=-4mA; VCC=4.5V | 4 | ||
| Low Level Output Voltage CMOS Loads (25°C) | VOL | 0.1 | V | IO=0.02mA; VI=VIH or VIL; VCC=4.5V | 4 | ||
| Low Level Output Voltage CMOS Loads (-40°C to 85°C) | VOL | 0.1 | V | IO=0.02mA; VI=VIH or VIL; VCC=4.5V | 4 | ||
| Low Level Output Voltage CMOS Loads (-55°C to 125°C) | VOL | 0.1 | V | IO=0.02mA; VI=VIH or VIL; VCC=4.5V | 4 | ||
| Low Level Output Voltage TTL Loads (25°C) | VOL | 0.26 | V | IO=4mA; VCC=4.5V | 4 | ||
| Low Level Output Voltage TTL Loads (-40°C to 85°C) | VOL | 0.33 | V | IO=4mA; VCC=4.5V | 4 | ||
| Low Level Output Voltage TTL Loads (-55°C to 125°C) | VOL | 0.4 | V | IO=4mA; VCC=4.5V | 4 | ||
| Input Leakage Current (25°C) | II | -0.1 | 0.1 | µA | VI=VCC and GND; VCC=5.5V | 4 | |
| Input Leakage Current (-40°C to 85°C) | II | -1 | 1 | µA | VI=VCC and GND; VCC=5.5V | 4 | |
| Input Leakage Current (-55°C to 125°C) | II | -1 | 1 | µA | VI=VCC and GND; VCC=5.5V | 4 | |
| Quiescent Device Current (25°C) | ICC | 2 | µA | VI=VCC or GND; VCC=5.5V | 4 | ||
| Quiescent Device Current (-40°C to 85°C) | ICC | 20 | µA | VI=VCC or GND; VCC=5.5V | 4 | ||
| Quiescent Device Current (-55°C to 125°C) | ICC | 40 | µA | VI=VCC or GND; VCC=5.5V | 4 | ||
| Additional Quiescent Device Current per Input Pin: 1 Unit Load (25°C) | ΔICC | 100 | 360 | µA | VI=VCC-2.1V; VCC=4.5 to 5.5V | 4 | |
| Additional Quiescent Device Current per Input Pin: 1 Unit Load (-40°C to 85°C) | ΔICC | 450 | µA | VI=VCC-2.1V; VCC=4.5 to 5.5V | 4 | ||
| Additional Quiescent Device Current per Input Pin: 1 Unit Load (-55°C to 125°C) | ΔICC | 490 | µA | VI=VCC-2.1V; VCC=4.5 to 5.5V | 4 | ||
| Propagation Delay, Input to Output (25°C) | tPLH, tPHL | 28 | ns | CL=50pF; VCC=4.5V; input tr, tf=6ns; Figure 2 | 5 | ||
| Propagation Delay, Input to Output (-40°C to 85°C) | tPLH, tPHL | 35 | ns | CL=50pF; VCC=4.5V; input tr, tf=6ns; Figure 2 | 5 | ||
| Propagation Delay, Input to Output (-55°C to 125°C) | tPLH, tPHL | 42 | ns | CL=50pF; VCC=4.5V; input tr, tf=6ns; Figure 2 | 5 | ||
| Transition Times (25°C) | tTLH, tTHL | 15 | ns | CL=50pF; VCC=4.5V; input tr, tf=6ns; Figure 2 | 5 | ||
| Transition Times (-40°C to 85°C) | tTLH, tTHL | 19 | ns | CL=50pF; VCC=4.5V; input tr, tf=6ns; Figure 2 | 5 | ||
| Transition Times (-55°C to 125°C) | tTLH, tTHL | 22 | ns | CL=50pF; VCC=4.5V; input tr, tf=6ns; Figure 2 | 5 | ||
| Input Capacitance (25°C) | CI | 10 | pF | CL=50pF | 5 | ||
| Input Capacitance (-40°C to 85°C) | CI | 10 | pF | CL=50pF | 5 | ||
| Input Capacitance (-55°C to 125°C) | CI | 10 | pF | CL=50pF | 5 | ||
| Supply Voltage Range, HCT Types | VCC | 4.5 | 5.5 | V | HCT types | 3 | |
| Operating Temperature Range | TA | -55 | 125 | °C | 3 | ||
| DC Input or Output Voltage | VI, VO | 0 | V | Maximum is VCC (not a printed number) | 3 | ||
| Input Rise and Fall Time | tr, tf | 500 | ns | VCC=4.5V | 3 | ||
| DC Supply Voltage | VCC | -0.5 | 7 | V | 3 | ||
| DC Input Diode Current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC + 0.5V | 3 | |
| DC Output Diode Current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC + 0.5V | 3 | |
| DC Output Source or Sink Current per Output Pin | IO | -25 | 25 | mA | VO > -0.5V or VO < VCC + 0.5V | 3 | |
| DC VCC or Ground Current | ICC or IGND | -50 | 50 | mA | 3 | ||
| Maximum Storage Temperature Range | Tstg | -65 | 150 | °C | 3 | ||
| Maximum Junction Temperature (Plastic Package) | TJ | 150 | °C | 3 | |||
| Maximum Lead Temperature (Soldering) | TLEAD | 300 | °C | 10s; SOIC lead tips only | 3 | ||
| Thermal Resistance, Junction to Ambient (M SOIC package) | θJA | 86 | °C/W | Typical, per JESD 51-7 (Note 1) | 3 |
CAD (KiCad official)
- Symbol:
CD74HCT11M96 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
cd74hct11m96-etched.step/cd74hct11m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hct11m96.step/cd74hct11m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (15 pp, sha256
95749b69c93f6059, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).