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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

BQ25504RGTR

Texas Instruments · Battery Management ICs · VQFN-16-EP(3x3)

BQ25504RGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VSS	power_in	General ground connection for the device; connect to thermal pad, with at least a 4.7 µF capacitor from VIN_DC and from VSTOR to this pin.
2	VIN_DC	power_in	DC voltage input from energy harvesters; connect at least a 4.7 µF capacitor as close as possible between this pin and pin 1, and a 22 µH inductor to LBST.
3	VOC_SAMP	input	MPPT sampling pin; connect to the mid-point of a resistor divider between VIN_DC and GND to set the MPP threshold voltage, or connect to VSTOR to disable the MPPT sampling circuit.
4	VREF_SAMP	input	Connect a 0.01 µF low-leakage capacitor to GND to store the MPPT sampled voltage to which VIN_DC is regulated; use an external voltage source when MPPT is disabled, or tie to GND to disable input voltage regulation.
5	OT_PROG	input	Digital programming input for the IC overtemperature threshold; connect to GND for the 60 C threshold or to VSTOR for the 120 C threshold.
6	VBAT_OV	input	Connect to the mid-point of a resistor divider between VRDIV and GND to set the VSTOR = VBAT overvoltage threshold.
7	VRDIV	output	Resistor divider biasing voltage.
8	VBAT_UV	input	Connect to the mid-point of a resistor divider between VRDIV and GND to set the VBAT undervoltage threshold; the PFET between VBAT and VSTOR opens if VSTOR is below this threshold.
9	OK_HYST	input	Connect to the mid-point of a resistor divider between VRDIV and GND to set the VBAT_OK hysteresis threshold; connect to GND if not used.
10	OK_PROG	input	Connect to the mid-point of a resistor divider between VRDIV and GND to set the VBAT_OK threshold; connect to GND if not used.
11	VBAT_OK	output	Digital battery-good indicator output, internally referenced to the VSTOR voltage; leave floating if not used.
12	AVSS	power_in	Signal ground connection for the device; connect to thermal pad.
13	VSS	power_in	General ground connection for the device; connect to thermal pad.
14	VBAT	power_in	Connection for a rechargeable storage element with at least 100 µF of equivalent capacitance.
15	VSTOR	power_out	Boost charger output, typically connected to the system load; connect at least a 4.7 µF capacitor in parallel with a 0.1 µF capacitor close to this pin and pin 1 (VSS).
16	LBST	passive	Inductor connection for the boost charger switching node; connect a 22 µH inductor between this pin and pin 2 (VIN_DC).
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-16-EP(3x3)
Category	Power Management ICs
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage (pins)		-0.3		5.5	V	VIN_DC, VOC_SAMP, VREF_SAMP, VBAT_OV, VBAT_UV, VRDIV, OK_HYST, OK_PROG, VBAT_OK, VBAT, VSTOR, LBST	6
Peak Input Power	PIN_PK			400	mW		6
Operating junction temperature range	TJ	-40		125	°C		6
Storage temperature range	Tstg	-65		150	°C		6
ESD HBM	V(ESD)			2	kV	Human body model, all pins	6
ESD CDM	V(ESD)			500	V	Charged device model, all pins	6
DC input voltage into VIN_DC	VIN (DC)	0.13		3	V	Maximum input power ≤ 300 mW. Cold start has been completed	6
Battery voltage range	VBAT	2.5		5.25	V	VBAT_OV setting must be higher than VIN_DC	6
Input capacitance	CHVR	4.23	4.7	5.17	µF		6
Storage capacitance	CSTOR	4.23	4.7	5.17	µF		6
Battery pin capacitance or equivalent battery capacity	CBAT	100			µF		6
Sampled reference storage capacitance	CREF	9	10	11	nF		6
Total resistance for MPPT reference	ROC1 + ROC2	18	20	22	MΩ		6
Total resistance for setting reference voltage	ROK1 + ROK2 + ROK3	9	10	11	MΩ		6
Input inductance	LBST	19.8	22	24.2	µH		6
Operating free air ambient temperature	TA	-40		85	°C		6
Operating junction temperature	TJ	-40		105	°C		6
DC input voltage into VIN_DC	VIN(DC)	130		3000	mV	Cold-start completed	7
Peak current flowing from VIN into VIN_DC input	IIN(DC)		200	300	mA	0.5V < VIN < 3 V; VSTOR = 4.2 V	7
Input power range for normal charging	PIN	0.01		300	mW	VBAT > VIN_DC; VIN_DC = 0.5 V	7
Cold-start voltage	VIN(CS)		600	700	mV	VBAT < VBAT_UV; VSTOR = 0 V; 0°C < TA < 85°C	7
Voltage on VSTOR when cold start ends	VSTOR_CHGEN	1.6	1.77	1.95	V		7
Leakage on VBAT pin (25°C)	IVBAT		1	5	nA	VBAT = 2.1 V; VBAT_UV = 2.3 V, TJ = 25°C, VSTOR = 0 V	7
Leakage on VBAT pin (over temp)	IVBAT			80	nA	VBAT = 2.1 V; VBAT_UV = 2.3 V, -40°C < TJ < 65°C, VSTOR = 0 V	7
VSTOR quiescent current, UV condition	IVSTOR		330	750	nA	VIN_DC = 0V; VBAT < VBAT_UV = 2.4V; VSTOR = 2.2V, No load on VBAT	7
VSTOR quiescent current, OV condition	IVSTOR		570	1400	nA	VIN_DC = 0V, VBAT > VBAT_OV, VSTOR = 4.25, No load on VBAT	7
Programmable overvoltage threshold range	VBAT_OV	2.5		5.25	V	VSTOR increasing	7
Battery overvoltage hysteresis	VBAT_OV_HYST	18	35	89	mV	VSTOR decreasing	7
Programmable undervoltage threshold range	VBAT_UV	2.2			V	VSTOR decreasing; VBAT_UV > VBias; upper limit VBAT_OV	7
Battery undervoltage hysteresis	VBAT_UV_HYST	40	80	125	mV	VSTOR increasing	7
Overall accuracy for thresholds UV, OV, VBAT_OK	VBAT_ACCURACY	-5		5	%	Selected resistors are 0.1% tolerance	7
VIN_DC regulation during charging	VIN_Reg	-10		10	%	0.5 V <VIN < 3 V; IIN (DC) = 10 mA	8
DC input voltage when charger turned off	VIN_shutoff	40	80	130	mV		8
Bias voltage reference	VBIAS	1.21	1.25	1.27	V	VIN_DC ≥ 0.5V; VSTOR ≥ 1.8 V	8
VBAT OK (Low) threshold voltage	VBAT_OKL			100	mV	Load = 10 µA	8
Minimum cold-start input power	PIN(CS)		15		µW	VBAT < VSTOR(CHGEN); VIN_DC clamped to VIN_CS by cold start circuit; VBAT = 100 µF ceramic	7
Resistance of switch between VBAT and VSTOR	RBAT(on)		2		Ω	VBAT = 4.2 V; VSTOR load = 50 mA	7
Charger low side switch ON resistance	RDS(on)		2		Ω	VBAT = 2.1 V / 4.2 V	7
Charger rectifier high side switch ON resistance	RDS(on)		5		Ω	VBAT = 2.1 V / 4.2 V	7
Boost converter switching frequency	fSW_BST		1		MHz		7
Overtemperature shutdown, OT_Prog = LO	TSD_PROTL		65		°C	OT_Prog = LO	8
Overtemperature shutdown, OT_Prog = HI	TSD_PROTH		120		°C	OT_Prog = HI	8
Voltage for OT_PROG High setting	OT_Prog	2			V		8
Voltage for OT_PROG Low setting	OT_Prog			0.3	V		8
Sampling period of VIN_DC open circuit voltage	VOC_sample		16		s		8
Settling period of VIN_DC open circuit voltage	VOC_Settling		256		ms		8
Junction-to-ambient thermal resistance	RθJA		48.5		°C/W	RGT (QFN) 16 pins	7
Junction-to-case (top) thermal resistance	RθJC(top)		63.9		°C/W		7
Junction-to-board thermal resistance	RθJB		22		°C/W		7
Junction-to-top characterization parameter	ψJT		1.8		°C/W		7
Junction-to-board characterization parameter	ψJB		22		°C/W		7
Junction-to-case (bottom) thermal resistance	RθJC(bot)		6.5		°C/W		7

CAD (KiCad official)

Symbol: BQ25504RGTR
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
3D model files: bq25504rgtr-etched.step / bq25504rgtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq25504rgtr.step / bq25504rgtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (38 pp, sha256 971c8f2e3296bf39, retrieved 2026-10-23, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF